linux-kernel - Re: [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support

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Message-ID: <CAJ9a7VjHHkkTz9XJqjdQ+11_XX9zXuY0ZcQzPtq=Zvi4CN__0A@mail.gmail.com>
Date: Thu, 4 Dec 2025 16:17:35 +0000
From: Mike Leach <mike.leach@...aro.org>
To: Leo Yan <leo.yan@....com>
Cc: Yingchao Deng <yingchao.deng@....qualcomm.com>, 
	Suzuki K Poulose <suzuki.poulose@....com>, James Clark <james.clark@...aro.org>, 
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>, 
	Tingwei Zhang <tingwei.zhang@....qualcomm.com>, quic_yingdeng@...cinc.com, 
	coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
	Jinlong Mao <jinlong.mao@....qualcomm.com>, Mao Jinlong <quic_jinlmao@...cinc.com>
Subject: Re: [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support

Hi Leo

On Thu, 4 Dec 2025 at 10:31, Leo Yan <leo.yan@....com> wrote:
>
> On Thu, Dec 04, 2025 at 09:07:56AM +0000, Mike Leach wrote:
>
> [...]
>
> > > I saw CTI registers are within 4KiB (0x1000), we can don't convert
> > > standard regiserts and only convert to QCOM register based on the
> > > standard ones.  So you can drop the cti_normal_offset strucuture and
> > > only have a cti_reg_qcom_offset[] struct:
> > >
> > >   static const u32 cti_extended_offset[] = {
> > >         [CTIINTACK]             = QCOM_CTIINTACK,
> > >         [CTIAPPSET]             = QCOM_CTIAPPSET,
> > >         [CTIAPPCLEAR]           = QCOM_CTIAPPCLEAR,
> > >         [CTIAPPPULSE]           = QCOM_CTIAPPPULSE,
> > >         [CTIINEN]               = QCOM_CTIINEN,
> > >         ...
> > >   };
> > >
> >

The tables in the patch are

    [reg_type_array_index] = offset_address;

e.g.

  [INDEX_CTIINTACK]  = QCOM_CTIINTACK

which resolves to

 [1] = 0x020

where index is constant for a given register type,

As far as I can tell what you have suggested above is a table that is

  [std_addr_offset] = qcom_addr_offset;

e.g.

[CTIINTACK]             = QCOM_CTIINTACK,

which resolves to

[0x10]  = 0x020

which does not appear to work correctly?

The registers are sparsely spread across the memory map, so a simple
mapping does not work, even if we divide the original offset by 4 to
create a register number.

The largest standard offset we have is ITTRIGIN = 0xEF8, so assuming
the compiler allows us to sparselly populate the array (which I think
it does, along with some padding), we end up with an array of at least
0xEF8 elements, rather then the indexed 21?

Regards

Mike

> > I suggested the dual offset approach a couple of patchset revisions
> > ago as it actually simplifies the code & makes it more efficient. The
> > offset array in use is set during probe and the remaining code is then
> > common to both without lots of "if qcom else " occurences.
>
> AFAICS, we will handle the QCOM CTI particularly in three cases:
>
>   1) The register access;
>   2) The claim tag;
>   3) Sysfs attr is visible.
>
> Now we are discussing the reigster access.  As suggested, the
> "if qcom / else" is encapsulated (e.g., in cti_reg_addr_with_nr()), it
> will not spread out.
>
> I'd use standard registers by default and convert to non-standard ones
> only when needed.  A new "neutral" index layer seems redundant, as the
> existing standard register indexes already serve this purpose.
>
> For the sysfs attrs, it makes sense to use a central place to decide
> which knobs are only visible for QCOM CTI, otherwise, we also will not
> spread the condition check.
>
> I will reply separately for claim tag issue.
>
> Thanks,
> Leo


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK