linux-kernel - Re: [PATCH 1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output

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Message-ID: <0102019aea7aa358-97e812cb-8010-4699-9a0e-ec041d6d9316-000000@eu-west-1.amazonses.com>
Date: Thu, 4 Dec 2025 17:48:17 +0000
From: Derek Foreman <derek.foreman@...labora.com>
To: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>, 
	Vinod Koul <vkoul@...nel.org>, 
	Neil Armstrong <neil.armstrong@...aro.org>, 
	Heiko Stuebner <heiko@...ech.de>, 
	Dmitry Baryshkov <lumag@...nel.org>
Cc: kernel@...labora.com, linux-phy@...ts.infradead.org, 
	linux-arm-kernel@...ts.infradead.org, 
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL
 config for 461.10125 MHz output

On 12/3/25 5:54 PM, Cristian Ciocaltea wrote:
> Attempting to make use of the 1080p@...Hz HDMI mode with 10 bpc RGB on
> my Acer XV275K P3 monitor results in a blank image.  A similar behavior
> has been reported on Philips 279M1RV.

Hello,

I'm the Philips 279M1RV complaint, and this patch fixes the problem on 
that monitor for me.

Tested-by: Derek Foreman <derek.foreman@...labora.com>

Thanks,
Derek

> The faulty modeline is created by drm_gtf_mode_complex() based on the
> following EDID entry from the Standard Timings block:
>
>    GTF:  1920x1080  119.999987 Hz  16:9    138.840 kHz    368.759000 MHz
>
> It's worth noting the computed pixel clock ends up being slightly higher
> at 368.881000 MHz.  Nevertheless, this seems to work consistently fine
> with 8 bpc RGB.
>
> After switching to 10 bpc, the TMDS character rate expected for the mode
> increases to 461.101250 MHz, as per drm_hdmi_compute_mode_clock().
>
> Since there is no entry for this rate in the ropll_tmds_cfg table, the
> necessary HDMI PLL configuration parameters are calculated dynamically
> by rk_hdptx_phy_clk_pll_calc().  However, the resulting output rate is
> not quite a perfect match, i.e. 461.100000 MHz, that proved to be the
> actual root cause of the problem.
>
> Add a new entry to the TMDS configuration table and provide the
> necessary frequency division coefficients for the PHY PLL to generate
> the expected 461.101250 MHz output.
>
> Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
> ---
>   drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 29de2f7bdae8..cafa618d70fd 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -414,6 +414,8 @@ struct rk_hdptx_phy {
>   static const struct ropll_config ropll_tmds_cfg[] = {
>   	{ 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
>   	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
> +	{ 461101250ULL, 97, 97, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 71, 1, 53, 2, 6,
> +	  35, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
>   	{ 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
>   	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
>   	{ 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
>