linux-kernel - Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop

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Message-Id: <DEP4X1DAIOU5.2WLIV4BMWLMRR@ventanamicro.com>
Date: Thu, 04 Dec 2025 13:07:20 +0900
From: Radim Krčmář <rkrcmar@...tanamicro.com>
To: "Yunhui Cui" <cuiyunhui@...edance.com>, <conor@...nel.org>,
 <paul.walmsley@...ive.com>, <palmer@...belt.com>, <aou@...s.berkeley.edu>,
 <alex@...ti.fr>, <luxu.kernel@...edance.com>,
 <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
 <jassisinghbrar@...il.com>, <conor.dooley@...rochip.com>,
 <valentina.fernandezalanis@...rochip.com>, <catalin.marinas@....com>,
 <will@...nel.org>, <maz@...nel.org>, <timothy.hayes@....com>,
 <lpieralisi@...nel.org>, <arnd@...db.de>, <kees@...nel.org>,
 <tglx@...utronix.de>, <viresh.kumar@...aro.org>, <boqun.feng@...il.com>,
 <linux-arm-kernel@...ts.infradead.org>, <cleger@...osinc.com>,
 <atishp@...osinc.com>, <ajones@...tanamicro.com>
Cc: "linux-riscv" <linux-riscv-bounces@...ts.infradead.org>
Subject: Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop

2025-11-27T20:53:02+08:00, Yunhui Cui <cuiyunhui@...edance.com>:
> Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> ---
> diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/riscv/riscv_sse_nmi.c
> @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
>  	type = atomic_read(this_cpu_ptr(&local_nmi));
>  
>  	NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs);
> +	NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop);

Please document the intended preemption design for all SSE events,
because it will be a nightmare if we forget some assumptions in the
coming years.  (That includes the relative priorities of RAS/PMU/...)

Thanks.