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Message-ID: <5095de61-69e8-4ef9-9604-702db46caee5@oss.qualcomm.com>
Date: Thu, 4 Dec 2025 15:46:16 +0800
From: Jie Luo <jie.luo@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
quic_kkumarcs@...cinc.com, quic_linchen@...cinc.com,
quic_leiwei@...cinc.com, quic_pavir@...cinc.com,
quic_suruchia@...cinc.com
Subject: Re: [PATCH 4/5] arm64: dts: ipq5332: Add CMN PLL node for networking
hardware
On 12/1/2025 9:52 PM, Konrad Dybcio wrote:
> On 11/28/25 9:40 AM, Luo Jie wrote:
>> Add the CMN PLL node required for networking hardware operation on IPQ5332.
>> The CMN PLL core runs at 6 GHz on this platform, differing from others like
>> IPQ9574.
>>
>> Configure the reference clock path where XO (48 MHz or 96 MHz) routes
>> through the WiFi block's multiplier/divider to provide a stable 48 MHz
>> reference to the CMN PLL.
>> .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.
>>
>> Signed-off-by: Luo Jie <jie.luo@....qualcomm.com>
>> ---
>
> [...]
>
>> + cmn_pll: clock-controller@...00 {
>> + compatible = "qcom,ipq5332-cmn-pll";
>> + reg = <0x0009b000 0x800>;
>> + clocks = <&ref_48mhz_clk>,
>> + <&gcc GCC_CMN_12GPLL_AHB_CLK>,
>> + <&gcc GCC_CMN_12GPLL_SYS_CLK>;
>> + clock-names = "ref", "ahb", "sys";
>
> 1 a line, please
OK, Will update, thanks.>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>
> Konrad
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