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Message-ID: <xvkh657hkoztrvyjrepmq3bvhmjfw6evwl27vski3547mgbnrq@wzok7ld4wmh6>
Date: Fri, 5 Dec 2025 22:14:43 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Abel Vesa <abel.vesa@....qualcomm.com>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Abel Vesa <abel.vesa@...aro.org>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v5 2/4] phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers
count
On Fri, Dec 05, 2025 at 04:23:21PM +0200, Abel Vesa wrote:
> From: Abel Vesa <abel.vesa@...aro.org>
>
> On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx
> registers. This hasn't been an issue so far on currently supported
> platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9.
>
> However, on the new upcoming Glymur platform, these are updated along
> with the rest of the init sequence.
>
> So update the size of the array holding the config to 13.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@....qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-edp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
--
With best wishes
Dmitry
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