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Message-ID: <221d5ed6-51da-4dce-b8a7-58b4d2423101@baylibre.com>
Date: Fri, 5 Dec 2025 17:43:31 -0600
From: David Lechner <dlechner@...libre.com>
To: Marcelo Schmitt <marcelo.schmitt1@...il.com>,
Rob Herring <robh@...nel.org>
Cc: Mark Brown <broonie@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Marcelo Schmitt <marcelo.schmitt@...log.com>,
Michael Hennerich <michael.hennerich@...log.com>,
Nuno Sá <nuno.sa@...log.com>,
Jonathan Cameron <jic23@...nel.org>, Andy Shevchenko <andy@...nel.org>,
Sean Anderson <sean.anderson@...ux.dev>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-iio@...r.kernel.org
Subject: Re: [PATCH v3 7/7] dt-bindings: iio: adc: adi,ad4030: add data-lanes
property
On 12/5/25 3:33 PM, David Lechner wrote:
> On 12/5/25 3:12 PM, Marcelo Schmitt wrote:
>> On 12/04, Rob Herring wrote:
>>> On Mon, Dec 01, 2025 at 08:20:45PM -0600, David Lechner wrote:
>>>> Add data-lanes property to specify the number of data lanes used on the
>>>> ad463x chips that support reading two samples at the same time using
>>>> two data lanes with a capable SPI controller.
>>>>
>>>> Signed-off-by: David Lechner <dlechner@...libre.com>
>>>> ---
>>>> v3 changes: new patch
>>>>
>>>> I added this one to give a real-world use case where spi-rx-bus-width
>>>> was not sufficient to fully describe the hardware configuration.
>>>>
>>>> spi-rx-bus-width = <4>; alone could be be interpreted as either:
>>>>
>>>> +--------------+ +----------+
>>>> | SPI | | AD4630 |
>>>> | Controller | | ADC |
>>>> | | | |
>>>> | SDIA0 |<---| SDOA0 |
>>>> | SDIA1 |<---| SDOA1 |
>>>> | SDIA2 |<---| SDOA2 |
>>>> | SDIA3 |<---| SDOA3 |
>>>> | | | |
>>>> | SDIB0 |x | SDOB0 |
>>>> | SDIB1 |x | SDOB1 |
>>>> | SDIB2 |x | SDOB2 |
>>>> | SDIB3 |x | SDOB3 |
>>>> | | | |
>>>> +--------------+ +---------+
>>>>
>>>> or
>>>>
>>>> +--------------+ +----------+
>>>> | SPI | | AD4630 |
>>>> | Controller | | ADC |
>>>> | | | |
>>>> | SDIA0 |<---| SDOA0 |
>>>> | SDIA1 |<---| SDOA1 |
>>>> | SDIA2 |x | SDOA2 |
>>>> | SDIA3 |x | SDOA3 |
>>>> | | | |
>>>> | SDIB0 |<---| SDOB0 |
>>>> | SDIB1 |<---| SDOB1 |
>>>> | SDIB2 |x | SDOB2 |
>>>> | SDIB3 |x | SDOB3 |
>>>> | | | |
>>>> +--------------+ +---------+
>>>>
>>>> Now, with data-lanes having a default value of [0] (inherited from
>>>> spi-peripheral-props.yaml), specifying:
>>>>
>>>> spi-rx-bus-width = <4>;
>>>>
>>>> is unambiguously the first case and the example given in the binding
>>>> documentation is the second case:
>>>>
>>>> spi-rx-bus-width = <2>;
>>>> data-lanes = <0>, <1>;
>>>
>>> I just reviewed this and all, but what if you just did:
>>>
>>> spi-rx-bus-width = <2>, <2>;
>>>
>>> So *-bus-width becomes equal to the number of serializers/channels.
>>
>> Unless I'm missing something, I think that would also describe the currently
>> possible use cases as well. To me, it actually seems even more accurate than
>> data-lanes. The data-lanes property only describes the SPI controller input
>> lines/lanes, no info is given about the output lanes.
>
> It describes both directions.
>
>> Well yeah, that would only> be a problem for a device with multiple input serializers and multiple output
>> serializers. Still, the *-bus-width = <N>, <N>, ... <N>; notation looks clearer,
>> IMHO.
>>
>>>
>>> Rob
>>>
>
> It think it complicates Sean's use case though where such
> a controller is being used as basically two separate SPI
> buses.
>
> For that case, we want to be able to do:
>
> spi {
> ...
>
> thing@0 {
> compatible = ...;
> reg = <0>;
> /* (implicit) data-lanes = <0>; */
> };
>
> thing@1 {
> compatible = ...;
> reg = <1>;
> data-lanes = <1>;
> };
> };
>
> Meaning:
>
> +--------------+ +----------+
> | SPI | | Thing 1 |
> | Controller | | |
> | | | |
> | CS0 |--->| CS |
> | SDI0 |<---| SDO |
> | SDO0 |--->| SDI |
> | SCLK0 |--->| SCLK |
> | | | |
> | | +----------+
> | |
> | | +----------+
> | | | Thing 2 |
> | | | |
> | CS1 |--->| CS |
> | SDI1 |<---| SDO |
> | SDO1 |--->| SDI |
> | SCLK1 |--->| SCLK |
> | | | |
> +--------------+ +----------+
>
> (I don't remember if SCLKs are shared or separate, but I don't
> think that is relevant anyway).
>
>
> I guess we could write it like this?
>
> spi {
> ...
>
> thing@0 {
> compatible = ...;
> reg = <0>;
> };
>
> thing@1 {
> compatible = ...;
> reg = <1>;
> spi-tx-bus-width = <0>, <1>;
> spi-rx-bus-width = <0>, <1>;
> };
> };
>
>
I started down this road. Before I do the working of changing the
whole series, this is what it will probably look like. Is this really
what we want?
There is one issue I see with this. If we allow <0> to mean that a lane
isn't wired up on the controller, then we can't constrain the length of
the array in peripheral bindings. For example, the ad403x chips can only
have one lane and the ad463x chips can have one or two lanes. But I
don't see a way to express that in the binding if <0> at any index
doesn't count towards the number of lanes that are actually wired up.
This is e.g. why the binding in sitronix,st7789v.yaml is
items:
enum: [0, 1]
rather than
items:
- enum: [0, 1]
---
commit 049b9508b1b0190f87a4b35fe3ed8a9f3d0d3c50
Author: David Lechner <dlechner@...libre.com>
Date: Fri Dec 5 16:09:08 2025 -0600
spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
Change spi-rx-bus-width and spi-tx-bus-width properties from single
uint32 values to arrays of uint32 values. This allows describing SPI
peripherals connected to controllers that have multiple data lanes for
receiving or transmitting two or more words at the same time.
Bindings that make use of this property are updated in the same commit
to avoid validation errors. Bindings that used minimum/maximum are
changed to use enum instead to be consistent with the base property
definition.
The adi,ad4030 binding has an example added now that we can fully
describe the peripheral's capabilities.
Converting from single uint32 to array of uint32 does not break .dts/
.dtb files since there is no difference between specifying a single
uint32 value and an array with a single uint32 value in devicetree.
Signed-off-by: David Lechner <dlechner@...libre.com>
---
diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
index 0ce2ea13583d..23b33dcd5ed4 100644
--- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
@@ -34,8 +34,8 @@ properties:
spi-cpol: true
spi-rx-bus-width:
- minimum: 0
- maximum: 1
+ items:
+ enum: [0, 1]
dc-gpios:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
index 54e7349317b7..6052a44b04de 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
@@ -37,7 +37,8 @@ properties:
maximum: 102040816
spi-rx-bus-width:
- enum: [1, 2, 4]
+ items:
+ enum: [1, 2, 4]
vdd-5v-supply: true
vdd-1v8-supply: true
@@ -108,3 +109,23 @@ examples:
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4630-24";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>, <4>;
+ vdd-5v-supply = <&supply_5V>;
+ vdd-1v8-supply = <&supply_1_8V>;
+ vio-supply = <&supply_1_8V>;
+ ref-supply = <&supply_5V>;
+ cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
index cbde7a0505d2..e15d985e8c59 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
@@ -38,8 +38,8 @@ properties:
spi-cpha: true
spi-rx-bus-width:
- minimum: 1
- maximum: 4
+ items:
+ enum: [1, 2, 4]
avdd-supply:
description: Analog power supply.
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
index e1ab3f523ad6..a34e6471dbe8 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
@@ -55,10 +55,12 @@ patternProperties:
maximum: 4
spi-rx-bus-width:
- const: 1
+ items:
+ - const: 1
spi-tx-bus-width:
- const: 1
+ items:
+ - const: 1
required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 3b47b68b92cb..414f5bc36304 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -77,10 +77,12 @@ patternProperties:
maximum: 4
spi-rx-bus-width:
- const: 1
+ items:
+ - const: 1
spi-tx-bus-width:
- const: 1
+ items:
+ - const: 1
required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 8b3640280559..909c204b8adf 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -54,10 +54,12 @@ patternProperties:
properties:
spi-rx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]
spi-tx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]
required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 8b6e8fc009db..6288740d8af3 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -64,9 +64,17 @@ properties:
description:
Bus width to the SPI bus used for read transfers.
If 0 is provided, then no RX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ receiving two or more words at the same time. If this is the case, each
+ index in the array represents the lane of the SPI controller. Lanes of
+ the peripheral are assumed to be connected in a logical order for each
+ non-zero entry in the array. Indexes where both spi-rx-bus-width and
+ spi-tx-bus-width are 0 are interpreted as not connected.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]
spi-rx-delay-us:
description:
@@ -81,9 +89,17 @@ properties:
description:
Bus width to the SPI bus used for write transfers.
If 0 is provided, then no TX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ transmitting two or more words at the same time. If this is the case, each
+ index in the array represents the lane of the SPI controller. Lanes of
+ the peripheral are assumed to be connected in a logical order for each
+ non-zero entry in the array. Indexes where both spi-rx-bus-width and
+ spi-tx-bus-width are 0 are interpreted as not connected.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]
spi-tx-delay-us:
description:
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