linux-kernel - RE: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

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Message-ID:
 <ZQ2PR01MB13076311CBBFE5B948F394FCE6A72@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn>
Date: Fri, 5 Dec 2025 07:41:49 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: Anand Moon <linux.amoon@...il.com>
CC: Conor Dooley <conor+dt@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Palmer Dabbelt
	<palmer@...belt.com>, Paul Walmsley <pjw@...nel.org>, Albert Ou
	<aou@...s.berkeley.edu>, "Rafael J . Wysocki" <rafael@...nel.org>, Viresh
 Kumar <viresh.kumar@...aro.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kwilczynski@...nel.org>, Manivannan
 Sadhasivam <mani@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Liam
 Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, Emil Renner
 Berthing <emil.renner.berthing@...onical.com>, Heinrich Schuchardt
	<heinrich.schuchardt@...onical.com>, E Shattow <e@...eshell.de>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for
 VisionFive 2 Lite variants

> On 05.12.25 01:05, Anand Moon wrote:
> Hi Hal,
> 
> On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@...rfivetech.com> wrote:
> >
> > Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2
> > Lite eMMC.
> >
> > Acked-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> > Tested-by: Matthias Brugger <mbrugger@...e.com>
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > ---
> >  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
> >  1 file changed, 161 insertions(+)
> >  create mode 100644
> > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> >
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > new file mode 100644
> > index 000000000000..f8797a666dbf
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.d
> > +++ tsi
> > @@ -0,0 +1,161 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@...rfivetech.com>  */
> > +
> > +/dts-v1/;
> > +#include "jh7110-common.dtsi"
> > +
> > +/ {
> > +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
> > +               compatible = "regulator-fixed";
> > +               enable-active-high;
> > +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > +               regulator-name = "vcc_3v3_pcie";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +       };
> > +};
> 
> The vcc_3v3_pcie regulator node is common to all JH7110 development
> boards.
> and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
> 
> VisionFive 2 Product Design Schematics below [1] https://doc-
> en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf
> 
> Mars_Hardware_Schematics
> [2] https://github.com/milkv-mars/mars-
> files/blob/main/Mars_Hardware_Schematics/Milk-
> V_Mars_SCH_V1.21_2024-0510.pdf

No, GPIO32 is connected to the WAKE pin, it is not used to control the PCIe slot power.

Best regards,
Hal