linux-kernel - Re: [PATCH 1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint

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Message-ID: <CAMyL0qMyRzpum2xeQ6rFGE+KR7jnEfQfyOQHb+5766tkOcBDrA@mail.gmail.com>
Date: Fri, 5 Dec 2025 19:18:23 +0530
From: Mrinmay Sarkar <mrinmay.sarkar@....qualcomm.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kwilczynski@...nel.org>,
        Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>, linux-arm-msm@...r.kernel.org,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, kernel@....qualcomm.com,
        Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
        Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>,
        quic_vbadigan@...cinc.com, quic_shazhuss@...cinc.com,
        konrad.dybcio@....qualcomm.com, Rama Krishna <quic_ramkri@...cinc.com>,
        Ayiluri Naga Rashmi <quic_nayiluri@...cinc.com>,
        Nitesh Gupta <quic_nitegupt@...cinc.com>
Subject: Re: [PATCH 1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document
 firmware managed PCIe endpoint

On Fri, Dec 5, 2025 at 6:44 PM Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
> On 05/12/2025 13:58, Mrinmay Sarkar wrote:
> >>>  1 file changed, 114 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
> >>> new file mode 100644
> >>> index 0000000000000000000000000000000000000000..970f65d46c8e2fa4c44665cb7a346dea1dc9e06a
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
> >>> @@ -0,0 +1,114 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Qualcomm firmware managed PCIe Endpoint Controller
> >>> +
> >>> +description:
> >>> +  Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys
> >>> +  DesignWare PCIe IP which is managed by firmware.
> >>> +
> >>> +maintainers:
> >>> +  - Manivannan Sadhasivam <mani@...nel.org>
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    const: qcom,sa8255p-pcie-ep
> >>> +
> >>> +  reg:
> >>> +    minItems: 6
> >>
> >> Why is this flexible?
> >
> > The reason for `minItems: 6` is that the DMA register space can be
> > skipped if DMA is not used.
>
> But the hardware has this anyway, so this must be here. You do not write
> bindings depending how drivers use them in your use case.
>
> Either drop minItems (fixed size of array) or provide rationale in terms
> of hardware in commit msg.
>
> ...

Thanks Krzysztof for the feedback.

 As per your suggestion, I will drop the `minItems` property for
`reg`, `reg-names`, `interrupts`, and `interrupt-names` since the
hardware always exposes all regions and interrupt lines.

I will use a fixed-size array with `items` only.

-Mrinmay
>
>
> >>> +
> >>> +  dma-coherent: true
> >>> +
> >>> +  num-lanes:
> >>> +    default: 2
> >>
> >> Isn't this deducible from the compatible? Do you have have different
> >> PCIe controllers with different lanes?
> >
> > SA8255p has 2 pcie controllers(pcie0 and pcie1).
> > pcie0 supports 2 lanes, and pcie1 supports 4 lanes.
>
> That's ok, thanks.
>
>
> Best regards,
> Krzysztof