linux-kernel - [PATCH v4 2/3] pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu

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Message-ID: <20251205015428.643-3-ming.qian@oss.nxp.com>
Date: Fri,  5 Dec 2025 09:54:25 +0800
From: ming.qian@....nxp.com
To: linux-media@...r.kernel.org
Cc: mchehab@...nel.org,
	hverkuil-cisco@...all.nl,
	nicolas@...fresne.ca,
	benjamin.gaignard@...labora.com,
	p.zabel@...gutronix.de,
	sebastian.fricke@...labora.com,
	shawnguo@...nel.org,
	ulf.hansson@...aro.org,
	s.hauer@...gutronix.de,
	kernel@...gutronix.de,
	festevam@...il.com,
	linux-imx@....com,
	l.stach@...gutronix.de,
	Frank.li@....com,
	peng.fan@....com,
	eagle.zhou@....com,
	imx@...ts.linux.dev,
	linux-pm@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v4 2/3] pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu

From: Ming Qian <ming.qian@....nxp.com>

For i.MX8MQ platform, the ADB in the VPUMIX domain has no separate reset
and clock enable bits, but is ungated and reset together with the VPUs.
So we can't reset G1 or G2 separately, it may led to the system hang.
Remove rst_mask and clk_mask of imx8mq_vpu_blk_ctl_domain_data.
Let imx8mq_vpu_power_notifier() do really vpu reset.

Fixes: 608d7c325e85 ("soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl")
Signed-off-by: Ming Qian <ming.qian@....nxp.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@...labora.com>
Reviewed-by: Peng Fan <peng.fan@....com>
Reviewed-by: Frank Li <Frank.Li@....com>
---
v3
- Add some comments
v2
- Update commit message

 drivers/pmdomain/imx/imx8m-blk-ctrl.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pmdomain/imx/imx8m-blk-ctrl.c b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
index 5c83e5599f1e..74bf4936991d 100644
--- a/drivers/pmdomain/imx/imx8m-blk-ctrl.c
+++ b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
@@ -846,22 +846,25 @@ static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
 	return NOTIFY_OK;
 }
 
+/*
+ * For i.MX8MQ, the ADB in the VPUMIX domain has no separate reset and clock
+ * enable bits, but is ungated and reset together with the VPUs.
+ * Resetting G1 or G2 separately may led to system hang.
+ * Remove the rst_mask and clk_mask from the domain data of G1 and G2,
+ * Let imx8mq_vpu_power_notifier() do really vpu reset.
+ */
 static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
 	[IMX8MQ_VPUBLK_PD_G1] = {
 		.name = "vpublk-g1",
 		.clk_names = (const char *[]){ "g1", },
 		.num_clks = 1,
 		.gpc_name = "g1",
-		.rst_mask = BIT(1),
-		.clk_mask = BIT(1),
 	},
 	[IMX8MQ_VPUBLK_PD_G2] = {
 		.name = "vpublk-g2",
 		.clk_names = (const char *[]){ "g2", },
 		.num_clks = 1,
 		.gpc_name = "g2",
-		.rst_mask = BIT(0),
-		.clk_mask = BIT(0),
 	},
 };
 
-- 
2.52.0