linux-kernel - Re: [PATCH 1/2] PCI: rzg3s-host: Use pci_generic_config

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Message-ID: <a9b02517-0743-4716-8ffe-e2120d9c611a@oss.qualcomm.com>
Date: Sat, 6 Dec 2025 06:59:28 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Claudiu <claudiu.beznea@...on.dev>, bhelgaas@...gle.com,
        lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
        robh@...nel.org
Cc: linux-pci@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea.uj@...renesas.com>,
        Bjorn Helgaas <helgaas@...nel.org>
Subject: Re: [PATCH 1/2] PCI: rzg3s-host: Use pci_generic_config_write() for
 the root bus



On 12/5/2025 4:54 PM, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> The Renesas RZ/G3S host controller allows writing to read-only PCIe
> configuration registers when the RZG3S_PCI_PERM_CFG_HWINIT_EN bit is set in
> the RZG3S_PCI_PERM register. However, callers of struct pci_ops::write
> expect the semantics defined by the PCIe specification, meaning that writes
> to read-only registers must not be allowed.
>
> The previous custom struct pci_ops::write implementation for the root bus
> temporarily enabled write access before calling pci_generic_config_write().
> This breaks the expected semantics.
>
> Remove the custom implementation and simply use pci_generic_config_write().
>
> Along with this change, the updates of the PCI_PRIMARY_BUS,
> PCI_SECONDARY_BUS, and PCI_SUBORDINATE_BUS registers were moved so that
> they no longer depends on the RZG3S_PCI_PERM_CFG_HWINIT_EN bit in the
> RZG3S_PCI_PERM_CFG register, since these registers are R/W.
>
Don't you need fixes tag and back port to stable kernels, this patch 
looks like a bug fix.

- Krishna Chaitanya.
> Suggested-by: Bjorn Helgaas <helgaas@...nel.org>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 27 ++++--------------------
>   1 file changed, 4 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 667e6d629474..547cbe676a25 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
>   	return host->pcie + where;
>   }
>   
> -/* Serialized by 'pci_lock' */
> -static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
> -				 int where, int size, u32 val)
> -{
> -	struct rzg3s_pcie_host *host = bus->sysdata;
> -	int ret;
> -
> -	/* Enable access control to the CFGU */
> -	writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
> -		       host->axi + RZG3S_PCI_PERM);
> -
> -	ret = pci_generic_config_write(bus, devfn, where, size, val);
> -
> -	/* Disable access control to the CFGU */
> -	writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> -
> -	return ret;
> -}
> -
>   static struct pci_ops rzg3s_pcie_root_ops = {
>   	.read		= pci_generic_config_read,
> -	.write		= rzg3s_pcie_root_write,
> +	.write		= pci_generic_config_write,
>   	.map_bus	= rzg3s_pcie_root_map_bus,
>   };
>   
> @@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
>   	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
>   	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
>   
> +	/* Disable access control to the CFGU */
> +	writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> +
>   	/* Update bus info */
>   	writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
>   	writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
>   	writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
>   
> -	/* Disable access control to the CFGU */
> -	writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> -
>   	return 0;
>   }
>