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Message-ID: <202512061720.j31AsgM7-lkp@intel.com>
Date: Sat, 6 Dec 2025 18:09:52 +0800
From: kernel test robot <lkp@...el.com>
To: dongxuyang@...incomputing.com, ukleinek@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, p.zabel@...gutronix.de,
linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: oe-kbuild-all@...ts.linux.dev, ningyu@...incomputing.com,
linmin@...incomputing.com, xuxiang@...incomputing.com,
wangguosheng@...incomputing.com, pinkesh.vaghela@...fochips.com,
Xuyang Dong <dongxuyang@...incomputing.com>
Subject: Re: [PATCH 2/2] pwm: eswin: Add EIC7700 pwm driver
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.18 next-20251205]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/dongxuyang-eswincomputing-com/dt-bindings-pwm-eswin-Add-EIC7700-pwm-controller/20251205-171328
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20251205090509.1501-1-dongxuyang%40eswincomputing.com
patch subject: [PATCH 2/2] pwm: eswin: Add EIC7700 pwm driver
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20251206/202512061720.j31AsgM7-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251206/202512061720.j31AsgM7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512061720.j31AsgM7-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/pwm/pwm-dwc-core.c: In function '__dwc_pwm_configure_timer':
>> drivers/pwm/pwm-dwc-core.c:54:43: warning: left shift count >= width of type [-Wshift-count-overflow]
54 | if (tmp < 0 || tmp > (1UL << 32))
| ^~
drivers/pwm/pwm-dwc-core.c:64:43: warning: left shift count >= width of type [-Wshift-count-overflow]
64 | if (tmp < 0 || tmp > (1UL << 32))
| ^~
vim +54 drivers/pwm/pwm-dwc-core.c
37
38 static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
39 struct pwm_device *pwm,
40 const struct pwm_state *state)
41 {
42 u64 tmp;
43 u32 ctrl;
44 u32 high;
45 u32 low;
46
47 if (dwc->pwm_0n100_enable) {
48 /*
49 * Calculate width of low and high period in terms of input
50 * clock periods and check are the result within HW limits
51 * between 0 and 2^32 periods.
52 */
53 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
> 54 if (tmp < 0 || tmp > (1UL << 32))
55 return -ERANGE;
56
57 if (pwm->args.polarity == PWM_POLARITY_INVERSED)
58 high = tmp;
59 else
60 low = tmp;
61
62 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
63 dwc->clk_ns);
64 if (tmp < 0 || tmp > (1UL << 32))
65 return -ERANGE;
66
67 if (pwm->args.polarity == PWM_POLARITY_INVERSED)
68 low = tmp;
69 else
70 high = tmp;
71 } else {
72 /*
73 * Calculate width of low and high period in terms of input
74 * clock periods and check are the result within HW limits
75 * between 1 and 2^32 periods.
76 */
77 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
78 if (tmp < 1 || tmp > (1ULL << 32))
79 return -ERANGE;
80 low = tmp - 1;
81
82 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
83 dwc->clk_ns);
84 if (tmp < 1 || tmp > (1ULL << 32))
85 return -ERANGE;
86 high = tmp - 1;
87 }
88
89 /*
90 * Specification says timer usage flow is to disable timer, then
91 * program it followed by enable. It also says Load Count is loaded
92 * into timer after it is enabled - either after a disable or
93 * a reset. Based on measurements it happens also without disable
94 * whenever Load Count is updated. But follow the specification.
95 */
96 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
97
98 /*
99 * Write Load Count and Load Count 2 registers. Former defines the
100 * width of low period and latter the width of high period in terms
101 * multiple of input clock periods:
102 * Width = ((Count + 1) * input clock period) or
103 * Width = (Count * input clock period) : supported 0% and 100%).
104 */
105 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
106 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
107
108 /*
109 * Set user-defined mode, timer reloads from Load Count registers
110 * when it counts down to 0.
111 * Set PWM mode, it makes output to toggle and width of low and high
112 * periods are set by Load Count registers.
113 */
114 ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
115 if (dwc->pwm_0n100_enable)
116 ctrl |= DWC_TIM_CTRL_0N100PWM_EN;
117
118 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
119
120 /*
121 * Enable timer. Output starts from low period.
122 */
123 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
124
125 return 0;
126 }
127
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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