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Message-ID: <aTXnKl2oCmrp11eq@tassilo>
Date: Sun, 7 Dec 2025 12:44:26 -0800
From: Andi Kleen <ak@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Dapeng Mi <dapeng1.mi@...ux.intel.com>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Jiri Olsa <jolsa@...nel.org>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Eranian Stephane <eranian@...gle.com>,
	Mark Rutland <mark.rutland@....com>, broonie@...nel.org,
	Ravi Bangoria <ravi.bangoria@....com>, linux-kernel@...r.kernel.org,
	linux-perf-users@...r.kernel.org, Zide Chen <zide.chen@...el.com>,
	Falcon Thomas <thomas.falcon@...el.com>,
	Dapeng Mi <dapeng1.mi@...el.com>, Xudong Hao <xudong.hao@...el.com>
Subject: Re: [Patch v5 16/19] perf/x86: Activate back-to-back NMI detection
 for arch-PEBS induced NMIs

On Fri, Dec 05, 2025 at 01:39:40PM +0100, Peter Zijlstra wrote:
> On Wed, Dec 03, 2025 at 02:54:57PM +0800, Dapeng Mi wrote:
> > When two or more identical PEBS events with the same sampling period are
> > programmed on a mix of PDIST and non-PDIST counters, multiple
> > back-to-back NMIs can be triggered.
> 
> This is a hardware defect -- albeit a fairly common one.

Actually I disagree on that. PEBS is essentially a shared memory
protocol between two asynchronous agents. To prevent this you would need a
locking protocol somehow for the memory, otherwise the sender (PEBS) has
no way to know that the PMI handler is finished reading the memory
buffers.

So it cannot know that the second event was already parsed, and
has to send the second PMI just in case.

It didn't happen with the legacy PEBS because it always 
collapsed multiple counters into one, but that was really a race
too.

-Andi

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