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Message-ID: <20251208-invisible-crazy-squirrel-bb3af0@quoll>
Date: Mon, 8 Dec 2025 07:29:50 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ye Zhang <ye.zhang@...k-chips.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Heiko Stuebner <heiko@...ech.de>, Bartosz Golaszewski <brgl@...ev.pl>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
tao.huang@...k-chips.com
Subject: Re: [PATCH v2 7/8] dt-bindings: pinctrl: rockchip: Add RMIO
controller binding
On Sat, Dec 06, 2025 at 01:08:43PM +0800, Ye Zhang wrote:
> Add device tree binding for the RMIO (Rockchip Matrix I/O) controller
> which is a sub-device of the main pinctrl on some Rockchip SoCs.
>
> Signed-off-by: Ye Zhang <ye.zhang@...k-chips.com>
> ---
> .../bindings/pinctrl/rockchip,pinctrl.yaml | 9 ++
> .../bindings/pinctrl/rockchip,rmio.yaml | 130 ++++++++++++++++++
> 2 files changed, 139 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
> index 93bf8f352e48..01df0a51ff83 100644
> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
> @@ -83,6 +83,15 @@ required:
> - rockchip,grf
>
> patternProperties:
> + "rmio[0-9]*$":
> + type: object
> +
> + $ref: "/schemas/pinctrl/rockchip,rmio.yaml#"
> +
> + description:
> + The RMIO (Rockchip Matrix I/O) controller node which functions as a
> + sub-device of the main pinctrl to handle flexible function routing.
> +
> "gpio@[0-9a-f]+$":
> type: object
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml
> new file mode 100644
> index 000000000000..28ec5ad62061
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/rockchip,rmio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RMIO (Rockchip Matrix I/O) Controller
> +
> +maintainers:
> + - Heiko Stuebner <heiko@...ech.de>
> +
> +description: |
> + The RMIO controller provides a flexible routing matrix that allows mapping
> + various internal peripheral functions (UART, SPI, PWM, etc.) to specific
> + physical pins. This block is typically a sub-block of the GRF
> + (General Register Files).
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rmio
Nope, you need Soc specific compatibles. Please see writing bindings
doc first.
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
Huh? That's already in the parent, no?
> + The phandle of the syscon node for the GRF registers.
> +
> + rockchip,offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + The offset of the RMIO configuration registers within the GRF.
> +
> + rockchip,pins-num:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + The number of physical pins supported by this RMIO instance.
> + Used for boundary checking and driver initialization.
> +
> +additionalProperties:
> + type: object
> + additionalProperties:
> + type: object
> + properties:
> + rockchip,rmio:
> + $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
> + description: |
> + A list of pin-function pairs. The format is <pin_id function_id>.
> + - pin_id: The index of the RMIO pin (0 to pins-num - 1).
> + - function_id: The mux value selecting the peripheral function.
> + minItems: 1
> + items:
> + items:
> + - minimum: 0
> + maximum: 31
> + description:
> + RMIO Pin ID.
> + - minimum: 0
> + maximum: 98
> + description:
> + Function ID.
> +
> + required:
> + - rockchip,rmio
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - rockchip,grf
> + - rockchip,offset
> + - rockchip,pins-num
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/pinctrl/rockchip.h>
> + #include <dt-bindings/pinctrl/rockchip,rk3506-rmio.h>
> +
> + pinctrl {
> + #address-cells = <1>;
> + #size-cells = <1>;
Drop all this and below. Parent node should have complete example.
> + ranges;
> +
> + rmio {
> + compatible = "rockchip,rmio";
> + rockchip,grf = <&grf_pmu>;
> + rockchip,offset = <0x80>;
> + rockchip,pins-num = <32>;
> +
> + rmio-uart {
> + rmio_pin27_uart1_tx: rmio-pin27-uart1-tx {
> + rockchip,rmio = <RMIO_PIN27 RMIO_UART1_TX>;
> + };
> +
> + rmio_pin28_uart1_rx: rmio-pin28-uart1-rx {
> + rockchip,rmio = <RMIO_PIN28 RMIO_UART1_RX>;
> + };
> + };
> + };
> +
> + pcfg_pull_default: pcfg-pull-default {
> + bias-pull-pin-default;
> + };
> +
> + rm {
> + rmio_pin27_pins: rmio-pin27-pins {
> + rockchip,pins = <1 RK_PC2 7 &pcfg-pull-default>;
> + };
> +
> + rmio_pin28_pins: rmio-pin28-pins {
> + rockchip,pins = <1 RK_PC3 7 &pcfg-pull-default>;
> + };
> + };
> + };
> +
> + uart1: serial@...64000 {
> + compatible = "snps,dw-apb-uart";
Do not add irrelevant examples. Please read carefully writing bindings,
writing schema and for example by talk for beginners in DT.
This patchset does not make me happy, too many trivial issues.
Best regards,
Krzysztof
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