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Message-ID: <5ddf6a43-da41-4720-a41c-1990fdb90a7e@oss.qualcomm.com>
Date: Mon, 8 Dec 2025 16:55:37 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Harshal Dev <harshal.dev@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Val Packett <val@...kett.cool>,
Stephan Gerhold <stephan.gerhold@...aro.org>,
Abel Vesa <abel.vesa@....qualcomm.com>,
Udit Tiwari <quic_utiwari@...cinc.com>,
Neeraj Soni <quic_neersoni@...cinc.com>
Subject: Re: [PATCH v4] arm64: dts: qcom: x1e80100: Add crypto engine
On 12/8/25 1:32 PM, Harshal Dev wrote:
> On X Elite, there is a crypto engine IP block similar to ones found on
> SM8x50 platforms.
>
> Describe the crypto engine and its BAM.
>
> Signed-off-by: Harshal Dev <harshal.dev@....qualcomm.com>
> ---
> The dt-binding schema update for the x1e80100 compatible is here
> (already merged):
>
> https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
> ---
> Changes in v4:
> - Updated iommu property to use 0x0 instead of 0x0000 in last cell.
> - Updated dma-names property by listing one dma channel name per line.
> - Use QCOM_ICC_TAG_ALWAYS symbol instead of 0 in the interconnects property.
> - Link to v3: https://lore.kernel.org/r/20251127-crypto_dt_node_x1e80100-v3-1-29722003fe83@oss.qualcomm.com
> ---
Thanks!
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Konrad
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