linux-kernel - Re: [PATCH v4] arm64: dts: qcom: x1e80100: Add crypto engine

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Message-ID: <ae9cd5b4-c33a-4757-805c-d817f1560b81@oss.qualcomm.com>
Date: Tue, 9 Dec 2025 14:41:40 +0800
From: Wenjia Zhang <wenjia.zhang@....qualcomm.com>
To: Harshal Dev <harshal.dev@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Val Packett <val@...kett.cool>,
        Stephan Gerhold <stephan.gerhold@...aro.org>,
        Abel Vesa <abel.vesa@....qualcomm.com>,
        Udit Tiwari <quic_utiwari@...cinc.com>,
        Neeraj Soni <quic_neersoni@...cinc.com>
Subject: Re: [PATCH v4] arm64: dts: qcom: x1e80100: Add crypto engine


在 8/12/2025 下午8:32, Harshal Dev 写道:
> On X Elite, there is a crypto engine IP block similar to ones found on
> SM8x50 platforms.
>
> Describe the crypto engine and its BAM.
>
> Signed-off-by: Harshal Dev <harshal.dev@....qualcomm.com>
> ---
> The dt-binding schema update for the x1e80100 compatible is here
> (already merged):
>      
> https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
> ---
> Changes in v4:
> - Updated iommu property to use 0x0 instead of 0x0000 in last cell.
> - Updated dma-names property by listing one dma channel name per line.
> - Use QCOM_ICC_TAG_ALWAYS symbol instead of 0 in the interconnects property.
> - Link to v3: https://lore.kernel.org/r/20251127-crypto_dt_node_x1e80100-v3-1-29722003fe83@oss.qualcomm.com
> ---
> Changes in v3:
> - Fixed num-channels and qcom,num-ees properties by updating them to 20 and 4 respectively.
> - Link to v2: https://lore.kernel.org/all/20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org
> Changes in v2:
> - Added EE and channels numbers in BAM node, like Stephan suggested.
> - Added v1.7.4 compatible as well.
> - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org
> ---
>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 51576d9c935d..0ae5242e98cb 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3033,6 +3033,32 @@ usb_1_ss2_qmpphy_dp_in: endpoint {
>   			};
>   		};
>   
> +		cryptobam: dma-controller@...4000 {
> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg = <0x0 0x01dc4000 0x0 0x28000>;
> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			iommus = <&apps_smmu 0x480 0x0>,
> +				 <&apps_smmu 0x481 0x0>;
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;
> +			num-channels = <20>;
> +			qcom,num-ees = <4>;
> +		};
> +
> +		crypto: crypto@...a000 {
> +			compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
> +			reg = <0x0 0x01dfa000 0x0 0x6000>;
> +			dmas = <&cryptobam 4>, <&cryptobam 5>;
> +			dma-names = "rx",
> +				    "tx";
> +			iommus = <&apps_smmu 0x480 0x0>,
> +				 <&apps_smmu 0x481 0x0>;
> +			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "memory";
> +		};
> +
>   		cnoc_main: interconnect@...0000 {
>   			compatible = "qcom,x1e80100-cnoc-main";
>   			reg = <0 0x01500000 0 0x14400>;
>
> ---
> base-commit: 765e56e41a5af2d456ddda6cbd617b9d3295ab4e
> change-id: 20251127-crypto_dt_node_x1e80100-bcb1a2837b56
>
> Best regards,

Tested-by: Wenjia Zhang <wenjia.zhang@....qualcomm.com> # on x1e80100

root@...ntu:/usr/Testools# ./kcapi-convenience.sh
[PASSED: 64-bit - 6.18.0-rc5] Convenience message digest operation
===================================================================
Number of failures: 0

Regards,
Wenjia