Message-ID: <176527657688.20066.3405220622225469005@freya>
Date: Tue, 09 Dec 2025 16:06:16 +0530
From: Jai Luthra <jai.luthra@...asonboard.com>
To: Rishikesh Donadkar <r-donadkar@...com>, Tomi Valkeinen <tomi.valkeinen@...asonboard.com>, jai.luthra@...ux.dev, laurent.pinchart@...asonboard.com, mripard@...nel.org
Cc: y-abhilashchandra@...com, devarsht@...com, s-jain1@...com, vigneshr@...com, mchehab@...nel.org, robh@...nel.org, krzk+dt@...nel.org, p.zabel@...gutronix.de, conor+dt@...nel.org, sakari.ailus@...ux.intel.com, hverkuil-cisco@...all.nl, changhuang.liang@...rfivetech.com, jack.zhu@...rfivetech.com, sjoerd@...labora.com, dan.carpenter@...aro.org, hverkuil+cisco@...nel.org, linux-kernel@...r.kernel.org, linux-media@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v8 13/18] media: ti: j721e-csi2rx: add multistream support

Hi Rishikesh,

Quoting Rishikesh Donadkar (2025-12-09 15:38:33)
> 
> On 01/12/25 18:33, Tomi Valkeinen wrote:
> > Hi,
> 
> 
> Hi Tomi,
> 
> Thank you for the review !
> 
> >
> > On 12/11/2025 13:54, Rishikesh Donadkar wrote:
> >> From: Jai Luthra <j-luthra@...com>
> >>
> >> Each CSI2 stream can be multiplexed into 4 independent streams, each
> > Well, that's not true, at least generally speaking (there can be more
> > than 4). Is that specific to TI hardware?
> 
> 
> Yes, The commit message talks about how TI CSI does the multiplexing of 
> CSI stream from the sensor into 4 streams as show in the Figure 12-388 
> in AM62A TRM[1]. I will modify the commit message to mention that this 
> is TI CSI specific.

Figure 12-388 shows the internal pixel stream coming from Cadence to
different hardware blocks like TI's Shim (DMA) and VP0 (ISP) and VP1. I
don't see that being related to CSI2 VC/DT support, which is handled by the
Shim using different DMA contexts and channels.

In the TRM, under 12.6.1.1.1 CSI_RX_IF Features, I see:
 * Compliant to MIPI CSI v1.3
 * Supports up to 16 virtual channels per input (partial MIPI CSI v2.0 feature)

So 16 VCs is supported by TI's CSI pipeline, despite it being MIPI CSI2
v1.3 compliant otherwise. I think I might have been confused with DS90UB960
while writing this commit message originally, which strictly supports a
maximum of 4 VCs.

Secondly, even with just CSI2 v1.0 compliant source, this could
theoretically handle 8 "streams" of data with 4 different VCs x 2 data
types each. So please update the paragraph in next revision.

Thanks,
    Jai

> 
> 
> [1]: 
> https://www.ti.com/lit/ug/spruj16c/spruj16c.pdf?ts=1765273774405&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAM62A7
> 
> 
> >
> >> identified by its virtual channel number and data type. The incoming
> >> data from these streams can be filtered on the basis of either the
> >> virtual channel or the data type.
> >>
> >> To capture this multiplexed stream, the application needs to tell
> >> the driver how it wants to route the data. It needs to specify
> >> which context should process which stream. This is done via the
> >> new routing APIs.
> >>
> >> Add ioctls to accept routing information from the application and save
> >> that in the driver. This can be used when starting streaming on a
> >> context to determine which route and consequently which virtual channel
> >> it should process.
> >>
> >> De-assert the pixel interface reset on first start_streaming() and assert
> >> it on the last stop_streaming().
> >>
> >> Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@...com>
> >> Co-developed-by: Pratyush Yadav <p.yadav@...com>
> >> Signed-off-by: Pratyush Yadav <p.yadav@...com>
> >> Signed-off-by: Jai Luthra <j-luthra@...com>
> >> Co-developed-by: Rishikesh Donadkar <r-donadkar@...com>
> >> Signed-off-by: Rishikesh Donadkar <r-donadkar@...com>
> >> ---
> >>   .../platform/ti/j721e-csi2rx/j721e-csi2rx.c   | 224 ++++++++++++++----
> >>   1 file changed, 179 insertions(+), 45 deletions(-)

[snip]

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