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Message-ID: <20251210003729.3909663-3-mr.nuke.me@gmail.com>
Date: Tue, 9 Dec 2025 18:37:24 -0600
From: Alexandru Gagniuc <mr.nuke.me@...il.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
Bjorn Andersson <andersson@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Placeholder Maintainer <placeholder@...nel.org>
Cc: konradybcio@...nel.org,
linux-arm-msm@...r.kernel.org,
linux-remoteproc@...r.kernel.org,
linux-kernel@...r.kernel.org,
Alexandru Gagniuc <mr.nuke.me@...il.com>
Subject: [PATCH RFC 2/3] dt-bindings: remoteproc: qcom: add IPQ9574 image loader
Document the IPQ9574 native (non-PAS) WCSS image loader. It is similar
to IPQ8074 WCSS, but requires several new clocks. These clocks must be
enabled in non-PAS mode, and are not optional. Add an example that
uses the "qcom,ipq9574-wcss-pil" binding.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@...il.com>
---
.../remoteproc/qcom,ipq9574-wcss-pil.yaml | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,ipq9574-wcss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,ipq9574-wcss-pil.yaml
index d28f42661d084..3daa1cb736bf2 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,ipq9574-wcss-pil.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,ipq9574-wcss-pil.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,ipq8074-wcss-pil
+ - qcom,ipq9574-wcss-pil
- qcom,qcs404-wcss-pil
reg:
@@ -112,6 +113,7 @@ allOf:
contains:
enum:
- qcom,ipq8074-wcss-pil
+ - qcom,ipq9574-wcss-pil
then:
properties:
qcom,smem-states:
@@ -136,6 +138,35 @@ allOf:
items:
- const: stop
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-wcss-pil
+ then:
+ properties:
+ clocks:
+ minItems: 13
+ clock-names:
+ items:
+ - const: anoc_wcss_axi_m
+ - const: wcss_ahb_s
+ - const: wcss_ecahb
+ - const: wcss_acmt
+ - const: wcss_axi_m
+ - const: q6_axim
+ - const: q6_axim2
+ - const: q6_ahb
+ - const: q6_ahb_s
+ - const: q6ss_boot
+ - const: mem_noc_q6_axi
+ - const: wcss_q6_tbu
+ - const: sys_noc_wcss_ahb
+ required:
+ - clocks
+ - clock-names
+
- if:
properties:
compatible:
@@ -165,3 +196,74 @@ allOf:
- cx-supply
additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+ q6v5_wcss: remoteproc@...0000 {
+ compatible = "qcom,ipq9574-wcss-pil";
+ reg = <0x0cd00000 0x4040>,
+ <0x004ab000 0x20>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
+ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ resets = <&gcc GCC_WCSSAON_RESET>,
+ <&gcc GCC_WCSS_BCR>,
+ <&gcc GCC_WCSS_Q6_BCR>;
+ reset-names = "wcss_aon_reset",
+ "wcss_reset",
+ "wcss_q6_reset";
+
+ clocks = <&gcc GCC_ANOC_WCSS_AXI_M_CLK>,
+ <&gcc GCC_WCSS_AHB_S_CLK>,
+ <&gcc GCC_WCSS_ECAHB_CLK>,
+ <&gcc GCC_WCSS_ACMT_CLK>,
+ <&gcc GCC_WCSS_AXI_M_CLK>,
+ <&gcc GCC_Q6_AXIM_CLK>,
+ <&gcc GCC_Q6_AXIM2_CLK>,
+ <&gcc GCC_Q6_AHB_CLK>,
+ <&gcc GCC_Q6_AHB_S_CLK>,
+ <&gcc GCC_Q6SS_BOOT_CLK>,
+ <&gcc GCC_MEM_NOC_Q6_AXI_CLK>,
+ <&gcc GCC_WCSS_Q6_TBU_CLK>,
+ <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>;
+
+ clock-names = "anoc_wcss_axi_m",
+ "wcss_ahb_s",
+ "wcss_ecahb",
+ "wcss_acmt",
+ "wcss_axi_m",
+ "q6_axim",
+ "q6_axim2",
+ "q6_ahb",
+ "q6_ahb_s",
+ "q6ss_boot",
+ "mem_noc_q6_axi",
+ "wcss_q6_tbu",
+ "sys_noc_wcss_ahb";
+
+ qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
+
+ qcom,smem-states = <&wcss_smp2p_out 0>,
+ <&wcss_smp2p_out 1>;
+ qcom,smem-state-names = "shutdown",
+ "stop";
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
--
2.45.1
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