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Message-Id: <20251210-profiles-v1-2-315a6ff2ca5a@gmail.com>
Date: Wed, 10 Dec 2025 08:13:39 -0800
From: Charlie Jenkins <charlie@...osinc.com>
To: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Alexandre Ghiti <alex@...ti.fr>, Anup Patel <anup@...infault.org>,
Atish Patra <atish.patra@...ux.dev>,
Samuel Holland <samuel.holland@...ive.com>,
Björn Töpel <bjorn@...nel.org>,
Luke Nelson <luke.r.nels@...il.com>, Xi Wang <xi.wang@...il.com>,
Eric Biggers <ebiggers@...nel.org>, Conor Dooley <conor@...nel.org>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Charlie Jenkins <thecharlesjenkins@...il.com>
Subject: [PATCH RFC 02/10] riscv: kconfig: Reorganize extensions
Move extension management out of the main riscv kconfig and into an
extension specific one. Since there are so many extensions in riscv,
listed them in a separate file can help to keep the kconfig files
organized.
Signed-off-by: Charlie Jenkins <thecharlesjenkins@...il.com>
---
arch/riscv/Kconfig | 335 +---------------------------------------
arch/riscv/Kconfig.extensions | 345 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 346 insertions(+), 334 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fadec20b87a8..22a6fed0b216 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -552,340 +552,7 @@ config RISCV_ALTERNATIVE_EARLY
help
Allows early patching of the kernel for special errata
-config RISCV_ISA_C
- bool "Emit compressed instructions when building Linux"
- default y
- help
- Adds "C" to the ISA subsets that the toolchain is allowed to emit
- when building Linux, which results in compressed instructions in the
- Linux binary. This option produces a kernel that will not run on
- systems that do not support compressed instructions.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_SUPM
- bool "Supm extension for userspace pointer masking"
- depends on 64BIT
- default y
- help
- Add support for pointer masking in userspace (Supm) when the
- underlying hardware extension (Smnpm or Ssnpm) is detected at boot.
-
- If this option is disabled, userspace will be unable to use
- the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API.
-
-config RISCV_ISA_SVNAPOT
- bool "Svnapot extension support for supervisor mode NAPOT pages"
- depends on 64BIT && MMU
- depends on RISCV_ALTERNATIVE
- default y
- help
- Enable support for the Svnapot ISA-extension when it is detected
- at boot.
-
- The Svnapot extension is used to mark contiguous PTEs as a range
- of contiguous virtual-to-physical translations for a naturally
- aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
- size. When HUGETLBFS is also selected this option unconditionally
- allocates some memory for each NAPOT page size supported by the kernel.
- When optimizing for low memory consumption and for platforms without
- the Svnapot extension, it may be better to say N here.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_SVPBMT
- bool "Svpbmt extension support for supervisor mode page-based memory types"
- depends on 64BIT && MMU
- depends on RISCV_ALTERNATIVE
- default y
- help
- Add support for the Svpbmt ISA-extension (Supervisor-mode:
- page-based memory types) in the kernel when it is detected at boot.
-
- The memory type for a page contains a combination of attributes
- that indicate the cacheability, idempotency, and ordering
- properties for access to that page.
-
- The Svpbmt extension is only available on 64-bit cpus.
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_HAS_V
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64imv)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv)
- depends on LD_IS_LLD || LD_VERSION >= 23800
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_V
- bool "Vector extension support"
- depends on TOOLCHAIN_HAS_V
- depends on FPU
- select DYNAMIC_SIGFRAME
- default y
- help
- Add support for the Vector extension when it is detected at boot.
- When this option is disabled, neither the kernel nor userspace may
- use vector procedures.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_V_DEFAULT_ENABLE
- bool "Enable userspace Vector by default"
- depends on RISCV_ISA_V
- default y
- help
- Say Y here if you want to enable Vector in userspace by default.
- Otherwise, userspace has to make explicit prctl() call to enable
- Vector, or enable it via the sysctl interface.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_V_UCOPY_THRESHOLD
- int "Threshold size for vectorized user copies"
- depends on RISCV_ISA_V
- default 768
- help
- Prefer using vectorized copy_to_user()/copy_from_user() when the
- workload size exceeds this value.
-
-config RISCV_ISA_V_PREEMPTIVE
- bool "Run kernel-mode Vector with kernel preemption"
- depends on PREEMPTION
- depends on RISCV_ISA_V
- default y
- help
- Usually, in-kernel SIMD routines are run with preemption disabled.
- Functions which invoke long running SIMD thus must yield the core's
- vector unit to prevent blocking other tasks for too long.
-
- This config allows the kernel to run SIMD without explicitly disabling
- preemption. Enabling this config will result in higher memory consumption
- due to the allocation of per-task's kernel Vector context.
-
-config RISCV_ISA_ZAWRS
- bool "Zawrs extension support for more efficient busy waiting"
- depends on RISCV_ALTERNATIVE
- default y
- help
- The Zawrs extension defines instructions to be used in polling loops
- which allow a hart to enter a low-power state or to trap to the
- hypervisor while waiting on a store to a memory location. Enable the
- use of these instructions in the kernel when the Zawrs extension is
- detected at boot.
-
-config TOOLCHAIN_HAS_ZABHA
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha)
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_ZABHA
- bool "Zabha extension support for atomic byte/halfword operations"
- depends on TOOLCHAIN_HAS_ZABHA
- depends on RISCV_ALTERNATIVE
- default y
- help
- Enable the use of the Zabha ISA-extension to implement kernel
- byte/halfword atomic memory operations when it is detected at boot.
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_HAS_ZACAS
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas)
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_ZACAS
- bool "Zacas extension support for atomic CAS"
- depends on RISCV_ALTERNATIVE
- default y
- help
- Enable the use of the Zacas ISA-extension to implement kernel atomic
- cmpxchg operations when it is detected at boot.
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_HAS_ZBB
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)
- depends on LD_IS_LLD || LD_VERSION >= 23900
- depends on AS_HAS_OPTION_ARCH
-
-# This symbol indicates that the toolchain supports all v1.0 vector crypto
-# extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once.
-# binutils added all except Zvkb, then added Zvkb. So we just check for Zvkb.
-config TOOLCHAIN_HAS_VECTOR_CRYPTO
- def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
- depends on AS_HAS_OPTION_ARCH
-
-config TOOLCHAIN_HAS_ZBA
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
- depends on LD_IS_LLD || LD_VERSION >= 23900
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_ZBA
- bool "Zba extension support for bit manipulation instructions"
- default y
- help
- Add support for enabling optimisations in the kernel when the Zba
- extension is detected at boot.
-
- The Zba extension provides instructions to accelerate the generation
- of addresses that index into arrays of basic data types.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_ZBB
- bool "Zbb extension support for bit manipulation instructions"
- depends on RISCV_ALTERNATIVE
- default y
- help
- Add support for enabling optimisations in the kernel when the
- Zbb extension is detected at boot. Some optimisations may
- additionally depend on toolchain support for Zbb.
-
- The Zbb extension provides instructions to accelerate a number
- of bit-specific operations (count bit population, sign extending,
- bitrotation, etc).
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_HAS_ZBC
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc)
- depends on LD_IS_LLD || LD_VERSION >= 23900
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_ZBC
- bool "Zbc extension support for carry-less multiplication instructions"
- depends on TOOLCHAIN_HAS_ZBC
- depends on MMU
- depends on RISCV_ALTERNATIVE
- default y
- help
- Adds support to dynamically detect the presence of the Zbc
- extension (carry-less multiplication) and enable its usage.
-
- The Zbc extension could accelerate CRC (cyclic redundancy check)
- calculations.
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_HAS_ZBKB
- bool
- default y
- depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbkb)
- depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb)
- depends on LD_IS_LLD || LD_VERSION >= 23900
- depends on AS_HAS_OPTION_ARCH
-
-config RISCV_ISA_ZBKB
- bool "Zbkb extension support for bit manipulation instructions"
- depends on TOOLCHAIN_HAS_ZBKB
- depends on RISCV_ALTERNATIVE
- default y
- help
- Adds support to dynamically detect the presence of the ZBKB
- extension (bit manipulation for cryptography) and enable its usage.
-
- The Zbkb extension provides instructions to accelerate a number
- of common cryptography operations (pack, zip, etc).
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_ZICBOM
- bool "Zicbom extension support for non-coherent DMA operation"
- depends on MMU
- depends on RISCV_ALTERNATIVE
- default y
- select RISCV_DMA_NONCOHERENT
- select DMA_DIRECT_REMAP
- help
- Add support for the Zicbom extension (Cache Block Management
- Operations) and enable its use in the kernel when it is detected
- at boot.
-
- The Zicbom extension can be used to handle for example
- non-coherent DMA support on devices that need it.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_ZICBOZ
- bool "Zicboz extension support for faster zeroing of memory"
- depends on RISCV_ALTERNATIVE
- default y
- help
- Enable the use of the Zicboz extension (cbo.zero instruction)
- in the kernel when it is detected at boot.
-
- The Zicboz extension is used for faster zeroing of memory.
-
- If you don't know what to do here, say Y.
-
-config RISCV_ISA_ZICBOP
- bool "Zicbop extension support for cache block prefetch"
- depends on MMU
- depends on RISCV_ALTERNATIVE
- default y
- help
- Adds support to dynamically detect the presence of the ZICBOP
- extension (Cache Block Prefetch Operations) and enable its
- usage.
-
- The Zicbop extension can be used to prefetch cache blocks for
- read/write fetch.
-
- If you don't know what to do here, say Y.
-
-config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
- def_bool y
- # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
- # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
- depends on AS_IS_GNU && AS_VERSION >= 23600
- help
- Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer
- 20191213 version, which moves some instructions from the I extension to
- the Zicsr and Zifencei extensions. This requires explicitly specifying
- Zicsr and Zifencei when binutils >= 2.38 or GCC >= 12.1.0. Zicsr
- and Zifencei are supported in binutils from version 2.36 onwards.
- To make life easier, and avoid forcing toolchains that default to a
- newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
- For clang < 17 or GCC < 11.3.0, for which this is not possible or need
- special treatment, this is dealt with in TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
-
-config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
- def_bool y
- depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
- # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
- # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d29f5d6ab513c52fd872f532c492e35ae9fd6671
- depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110300)
- help
- Certain versions of clang and GCC do not support zicsr and zifencei via
- -march. This option causes an older ISA spec compatible with these older
- versions of clang and GCC to be passed to GAS, which has the same result
- as passing zicsr and zifencei to -march.
-
-config FPU
- bool "FPU support"
- default y
- help
- Add support for floating point operations when an FPU is detected at
- boot. When this option is disabled, neither the kernel nor userspace
- may use the floating point unit.
-
- If you don't know what to do here, say Y.
+source "arch/riscv/Kconfig.extensions"
config IRQ_STACKS
bool "Independent irq & softirq stacks" if EXPERT
diff --git a/arch/riscv/Kconfig.extensions b/arch/riscv/Kconfig.extensions
new file mode 100644
index 000000000000..c9433209117d
--- /dev/null
+++ b/arch/riscv/Kconfig.extensions
@@ -0,0 +1,345 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.rst.
+#
+
+
+# Base extensions
+
+config RISCV_ISA_C
+ bool "Emit compressed instructions when building Linux"
+ default y
+ help
+ Adds "C" to the ISA subsets that the toolchain is allowed to emit
+ when building Linux, which results in compressed instructions in the
+ Linux binary.
+
+ If you don't know what to do here, say Y.
+
+config FPU
+ bool "FPU support"
+ default y
+ help
+ Say N here if you want to disable all floating-point related procedure
+ in the kernel.
+
+ If you don't know what to do here, say Y.
+
+# Standard extensions
+
+config RISCV_ISA_SUPM
+ bool "Supm extension for userspace pointer masking"
+ depends on 64BIT
+ default y
+ help
+ Add support for pointer masking in userspace (Supm) when the
+ underlying hardware extension (Smnpm or Ssnpm) is detected at boot.
+
+ If this option is disabled, userspace will be unable to use
+ the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API.
+
+config RISCV_ISA_SVNAPOT
+ bool "Svnapot extension support for supervisor mode NAPOT pages"
+ depends on 64BIT && MMU
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Allow kernel to detect the Svnapot ISA-extension dynamically at boot
+ time and enable its usage.
+
+ The Svnapot extension is used to mark contiguous PTEs as a range
+ of contiguous virtual-to-physical translations for a naturally
+ aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
+ size. When HUGETLBFS is also selected this option unconditionally
+ allocates some memory for each NAPOT page size supported by the kernel.
+ When optimizing for low memory consumption and for platforms without
+ the Svnapot extension, it may be better to say N here.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_SVPBMT
+ bool "Svpbmt extension support for supervisor mode page-based memory types"
+ depends on 64BIT && MMU
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the Svpbmt
+ ISA-extension (Supervisor-mode: page-based memory types) and
+ enable its usage.
+
+ The memory type for a page contains a combination of attributes
+ that indicate the cacheability, idempotency, and ordering
+ properties for access to that page.
+
+ The Svpbmt extension is only available on 64-bit cpus.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_ZAWRS
+ bool "Zawrs extension support for more efficient busy waiting"
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ The Zawrs extension defines instructions to be used in polling loops
+ which allow a hart to enter a low-power state or to trap to the
+ hypervisor while waiting on a store to a memory location. Enable the
+ use of these instructions in the kernel when the Zawrs extension is
+ detected at boot.
+
+config TOOLCHAIN_HAS_ZABHA
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha)
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZABHA
+ bool "Zabha extension support for atomic byte/halfword operations"
+ depends on TOOLCHAIN_HAS_ZABHA
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Enable the use of the Zabha ISA-extension to implement kernel
+ byte/halfword atomic memory operations when it is detected at boot.
+
+ If you don't know what to do here, say Y.
+
+config TOOLCHAIN_HAS_ZACAS
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas)
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZACAS
+ bool "Zacas extension support for atomic CAS"
+ depends on TOOLCHAIN_HAS_ZACAS
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Enable the use of the Zacas ISA-extension to implement kernel atomic
+ cmpxchg operations when it is detected at boot.
+
+ If you don't know what to do here, say Y.
+
+config TOOLCHAIN_HAS_ZBA
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
+ depends on LD_IS_LLD || LD_VERSION >= 23900
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZBA
+ bool "Zba extension support for bit manipulation instructions"
+ default y
+ help
+ Add support for enabling optimisations in the kernel when the Zba
+ extension is detected at boot.
+
+ The Zba extension provides instructions to accelerate the generation
+ of addresses that index into arrays of basic data types.
+
+ If you don't know what to do here, say Y.
+
+config TOOLCHAIN_HAS_ZBB
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)
+ depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZBB
+ bool "Zbb extension support for bit manipulation instructions"
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the ZBB
+ extension (basic bit manipulation) and enable its usage.
+
+ The Zbb extension provides instructions to accelerate a number
+ of bit-specific operations (count bit population, sign extending,
+ bitrotation, etc).
+
+ If you don't know what to do here, say Y.
+
+config TOOLCHAIN_HAS_ZBC
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc)
+ depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZBC
+ bool "Zbc extension support for carry-less multiplication instructions"
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the Zbc
+ extension (carry-less multiplication) and enable its usage.
+
+ The Zbc extension could accelerate CRC (cyclic redundancy check)
+ calculations.
+
+ If you don't know what to do here, say Y.
+
+config TOOLCHAIN_HAS_ZBKB
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbkb)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb)
+ depends on LD_IS_LLD || LD_VERSION >= 23900
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_ZBKB
+ tristate "Zbkb extension support for bit manipulation instructions"
+ depends on RISCV_ALTERNATIVE
+ depends on NONPORTABLE || m
+ default m
+ help
+ Adds support to dynamically detect the presence of the ZBKB
+ extension (bit manipulation for cryptography) and enable its usage.
+
+ The Zbkb extension provides instructions to accelerate a number
+ of common cryptography operations (pack, zip, etc).
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_ZICBOM
+ bool "Zicbom extension support for non-coherent DMA operation"
+ depends on MMU
+ depends on RISCV_ALTERNATIVE
+ default y
+ select RISCV_DMA_NONCOHERENT
+ select DMA_DIRECT_REMAP
+ help
+ Adds support to dynamically detect the presence of the ZICBOM
+ extension (Cache Block Management Operations) and enable its
+ usage.
+
+ The Zicbom extension can be used to handle for example
+ non-coherent DMA support on devices that need it.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_ZICBOZ
+ bool "Zicboz extension support for faster zeroing of memory"
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Enable the use of the Zicboz extension (cbo.zero instruction)
+ when available.
+
+ The Zicboz extension is used for faster zeroing of memory.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_ZICBOP
+ bool "Zicbop extension support for cache block prefetch"
+ depends on MMU
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the ZICBOP
+ extension (Cache Block Prefetch Operations) and enable its
+ usage.
+
+ The Zicbop extension can be used to prefetch cache blocks for
+ read/write fetch.
+
+ If you don't know what to do here, say Y.
+
+## Vector options
+
+config TOOLCHAIN_HAS_V
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64imv)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv)
+ depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
+ depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_V
+ bool "VECTOR extension support"
+ depends on TOOLCHAIN_HAS_V
+ depends on FPU
+ select DYNAMIC_SIGFRAME
+ default y
+ help
+ Say N here if you want to disable all vector related procedure
+ in the kernel.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_V_DEFAULT_ENABLE
+ bool "Enable userspace Vector by default"
+ depends on RISCV_ISA_V
+ default y
+ help
+ Say Y here if you want to enable Vector in userspace by default.
+ Otherwise, userspace has to make explicit prctl() call to enable
+ Vector, or enable it via the sysctl interface.
+
+ If you don't know what to do here, say Y.
+
+config RISCV_ISA_V_UCOPY_THRESHOLD
+ int "Threshold size for vectorized user copies"
+ depends on RISCV_ISA_V
+ default 768
+ help
+ Prefer using vectorized copy_to_user()/copy_from_user() when the
+ workload size exceeds this value.
+
+config RISCV_ISA_V_PREEMPTIVE
+ bool "Run kernel-mode Vector with kernel preemption"
+ depends on PREEMPTION
+ depends on RISCV_ISA_V
+ default y
+ help
+ Usually, in-kernel SIMD routines are run with preemption disabled.
+ Functions which envoke long running SIMD thus must yield core's
+ vector unit to prevent blocking other tasks for too long.
+
+ This config allows kernel to run SIMD without explicitly disable
+ preemption. Enabling this config will result in higher memory
+ consumption due to the allocation of per-task's kernel Vector context.
+
+# This symbol indicates that the toolchain supports all v1.0 vector crypto
+# extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once.
+# binutils added all except Zvkb, then added Zvkb. So we just check for Zvkb.
+config TOOLCHAIN_HAS_VECTOR_CRYPTO
+ def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
+ depends on AS_HAS_OPTION_ARCH
+
+# Legacy options
+
+config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
+ def_bool y
+ # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
+ # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
+ depends on AS_IS_GNU && AS_VERSION >= 23600
+ help
+ Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer
+ 20191213 version, which moves some instructions from the I extension to
+ the Zicsr and Zifencei extensions. This requires explicitly specifying
+ Zicsr and Zifencei when binutils >= 2.38 or GCC >= 12.1.0. Zicsr
+ and Zifencei are supported in binutils from version 2.36 onwards.
+ To make life easier, and avoid forcing toolchains that default to a
+ newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
+ For clang < 17 or GCC < 11.3.0, for which this is not possible or need
+ special treatment, this is dealt with in TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
+
+config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
+ def_bool y
+ depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
+ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
+ # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d29f5d6ab513c52fd872f532c492e35ae9fd6671
+ depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110300)
+ help
+ Certain versions of clang and GCC do not support zicsr and zifencei via
+ -march. This option causes an older ISA spec compatible with these older
+ versions of clang and GCC to be passed to GAS, which has the same result
+ as passing zicsr and zifencei to -march.
--
2.43.0
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