linux-kernel - Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU

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Message-ID: <20251211133723.GA859302-robh@kernel.org>
Date: Thu, 11 Dec 2025 07:37:23 -0600
From: Rob Herring <robh@...nel.org>
To: Jie Gan <jie.gan@....qualcomm.com>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
	Mike Leach <mike.leach@...aro.org>,
	James Clark <james.clark@...aro.org>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Tingwei Zhang <tingwei.zhang@....qualcomm.com>,
	Mao Jinlong <jinlong.mao@....qualcomm.com>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>, coresight@...ts.linaro.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
	Krzysztof Kozlowski <krzk@...nel.org>
Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for
 Coresight CTCU

On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote:
> Add an interrupt property to CTCU device. The interrupt will be triggered
> when the data size in the ETR buffer exceeds the threshold of the
> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
> of CTCU device will enable the interrupt.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Reviewed-by: Mike Leach <mike.leach@...aro.org>
> Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
> ---
>  .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..90f88cc6cd3e 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -39,6 +39,16 @@ properties:
>      items:
>        - const: apb
>  
> +  interrupts:
> +    items:
> +      - description: Byte cntr interrupt for the first etr device
> +      - description: Byte cntr interrupt for the second etr device
> +
> +  interrupt-names:
> +    items:
> +      - const: etrirq0
> +      - const: etrirq1

Names are kind of pointless when it is just foo<index>.

> +
>    label:
>      description:
>        Description of a coresight device.
> @@ -60,6 +70,8 @@ additionalProperties: false
>  
>  examples:
>    - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
>      ctcu@...1000 {
>          compatible = "qcom,sa8775p-ctcu";
>          reg = <0x1001000 0x1000>;
> @@ -67,6 +79,11 @@ examples:
>          clocks = <&aoss_qmp>;
>          clock-names = "apb";
>  
> +        interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
> +        interrupt-names = "etrirq0",
> +                          "etrirq1;
> +
>          in-ports {
>              #address-cells = <1>;
>              #size-cells = <0>;
> 
> -- 
> 2.34.1
>