linux-kernel - Re: [PATCH v3] mmc: sdhci-esdhc-imx: wait for data transfer completion before reset

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Message-ID: <fc3ffb7b-d2f4-4337-8086-8dcb146bfa07@intel.com>
Date: Fri, 12 Dec 2025 13:58:41 +0200
From: Adrian Hunter <adrian.hunter@...el.com>
To: <ziniu.wang_1@....com>, <haibo.chen@....com>, <ulf.hansson@...aro.org>
CC: <shawnguo@...nel.org>, <s.hauer@...gutronix.de>, <kernel@...gutronix.de>,
	<festevam@...il.com>, <linux-mmc@...r.kernel.org>, <imx@...ts.linux.dev>,
	<s32@....com>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] mmc: sdhci-esdhc-imx: wait for data transfer
 completion before reset

On 11/12/2025 09:56, ziniu.wang_1@....com wrote:
> From: Luke Wang <ziniu.wang_1@....com>
> 
> On IMX7ULP platforms, certain SD cards (e.g. Kingston Canvas Go! Plus)
> cause system hangs and reboots during manual tuning. These cards exhibit
> large gaps (~16us) between tuning command response and data transmission.
> When cmd CRC errors occur during tuning, the code assumes data errors even
> tuning data hasn't been fully received and then reset host data circuit.
> 
> Per IMX7ULP reference manual, reset operations (RESET_DATA/ALL) need to
> make sure no active data transfers. Previously, resetting while data was
> in-flight would clear data circuit, including ADMA/SDMA address, causing
> data to be transmitted to incorrect memory address. This patch adds
> polling for data transfer completion before executing resets.
> 
> Signed-off-by: Luke Wang <ziniu.wang_1@....com>
> Reviewed-by: Bough Chen <haibo.chen@....com>

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
> v3: add define for timeout value
> v2: amend commit message
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a7a5df673b0f..97461e20425d 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -216,6 +216,8 @@
>  #define ESDHC_FLAG_DUMMY_PAD		BIT(19)
>  
>  #define ESDHC_AUTO_TUNING_WINDOW	3
> +/* 100ms timeout for data inhibit */
> +#define ESDHC_DATA_INHIBIT_WAIT_US	100000
>  
>  enum wp_types {
>  	ESDHC_WP_NONE,		/* no WP, neither controller nor gpio */
> @@ -1453,6 +1455,22 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
>  
>  static void esdhc_reset(struct sdhci_host *host, u8 mask)
>  {
> +	u32 present_state;
> +	int ret;
> +
> +	/*
> +	 * For data or full reset, ensure any active data transfer completes
> +	 * before resetting to avoid system hang.
> +	 */
> +	if (mask & (SDHCI_RESET_DATA | SDHCI_RESET_ALL)) {
> +		ret = readl_poll_timeout_atomic(host->ioaddr + ESDHC_PRSSTAT, present_state,
> +						!(present_state & SDHCI_DATA_INHIBIT), 2,
> +						ESDHC_DATA_INHIBIT_WAIT_US);
> +		if (ret == -ETIMEDOUT)
> +			dev_warn(mmc_dev(host->mmc),
> +				 "timeout waiting for data transfer completion\n");
> +	}
> +
>  	sdhci_and_cqhci_reset(host, mask);
>  
>  	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);