linux-kernel - [PATCH RFC 0/4] Support multi-channel IRQs in stmmac platform drivers

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Message-Id: <20251214-dwmac_multi_irq-v1-0-36562ab0e9f7@oss.nxp.com>
Date: Sun, 14 Dec 2025 23:15:36 +0100
From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@...nel.org>
To: Andrew Lunn <andrew+netdev@...n.ch>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Chester Lin <chester62515@...il.com>, Matthias Brugger <mbrugger@...e.com>, 
 Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>, 
 NXP S32 Linux Team <s32@....com>, Shawn Guo <shawnguo@...nel.org>, 
 Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>
Cc: netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 imx@...ts.linux.dev, devicetree@...r.kernel.org, 
 "Jan Petrous (OSS)" <jan.petrous@....nxp.com>
Subject: [PATCH RFC 0/4] Support multi-channel IRQs in stmmac platform
 drivers

The stmmac core supports two interrupt modes, controlled by the
flag STMMAC_FLAG_MULTI_MSI_EN.
- When the flag is set, the driver uses multi-channel IRQ mode (multi-IRQ).
- Otherwise, a single IRQ line is requested:

static int stmmac_request_irq(struct net_device *dev)
{
        /* Request the IRQ lines */
        if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN)
                ret = stmmac_request_irq_multi_msi(dev);
        else
                ret = stmmac_request_irq_single(dev);
}

At present, only PCI drivers (Intel and Loongson) make use of the multi-IRQ
mode. This concept can be extended to DT-based embedded glue drivers
(dwmac-xxx.c).

This series adds support for reading per-channel IRQs from the DT node and
reuses the existing STMMAC_FLAG_MULTI_MSI_EN flag to enable multi-IRQ
operation in platform drivers.

NXP S32G2/S32G3/S32R SoCs integrate the DWMAC IP with multi-channel
interrupt support. The dwmac-s32.c driver change is provided as an example of
enabling multi-IRQ mode for non-PCI drivers.

An open question remains: should platform drivers support both single-IRQ
and multi-IRQ modes, or should multi-IRQ be required with the DT node
specifying all channel interrupts? The current RFC implementation follows
the latter approach — dwmac-s32 requires IRQs to be defined for all
channels.

So, when the glue driver has set the flag, but the corresponding DT node
has not expanded 'interrupts' property accordingly, the driver init
fails with the following error:

[4.925420] s32-dwmac 4033c000.ethernet eth0: stmmac_request_irq_multi_msi: alloc rx-0  MSI -6 (error: -22)

When correctly set, the assigned IRQs can be visible
in /proc/interrupts:

root@...g399aevb3:~# grep eth /proc/interrupts
 29:          0          0          0          0          0          0          0          0    GICv3  89 Level     eth0:mac
 30:          0          0          0          0          0          0          0          0    GICv3  91 Level     eth0:rx-0
 31:          0          0          0          0          0          0          0          0    GICv3  93 Level     eth0:rx-1
 32:          0          0          0          0          0          0          0          0    GICv3  95 Level     eth0:rx-2
 33:          0          0          0          0          0          0          0          0    GICv3  97 Level     eth0:rx-3
 34:          0          0          0          0          0          0          0          0    GICv3  99 Level     eth0:rx-4
 35:          0          0          0          0          0          0          0          0    GICv3  90 Level     eth0:tx-0
 36:          0          0          0          0          0          0          0          0    GICv3  92 Level     eth0:tx-1
 37:          0          0          0          0          0          0          0          0    GICv3  94 Level     eth0:tx-2
 38:          0          0          0          0          0          0          0          0    GICv3  96 Level     eth0:tx-3
 39:          0          0          0          0          0          0          0          0    GICv3  98 Level     eth0:tx-4

Signed-off-by: Jan Petrous (OSS) <jan.petrous@....nxp.com>
---
Jan Petrous (OSS) (4):
      net: stmmac: platform: read channels irq
      dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
      arm64: dts: s32: set Ethernet channel irqs
      stmmac: s32: enable multi irqs mode

 .../devicetree/bindings/net/nxp,s32-dwmac.yaml     | 40 +++++++++++++++++++---
 arch/arm64/boot/dts/freescale/s32g2.dtsi           | 24 +++++++++++--
 arch/arm64/boot/dts/freescale/s32g3.dtsi           | 24 +++++++++++--
 drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c    |  3 +-
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 38 +++++++++++++++++++-
 5 files changed, 119 insertions(+), 10 deletions(-)
---
base-commit: cb015814f8b6eebcbb8e46e111d108892c5e6821
change-id: 20251209-dwmac_multi_irq-9d8f60462cc1

Best regards,
-- 
Jan Petrous (OSS) <jan.petrous@....nxp.com>