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Message-ID: <7ebe3796-0bbb-449a-9c74-50f6907dec49@oss.qualcomm.com>
Date: Mon, 15 Dec 2025 16:46:28 +0800
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, aiqun.yu@....qualcomm.com,
tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
yijie.yang@....qualcomm.com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
phone-devel@...r.kernel.org,
Tengfei Fan <tengfei.fan@....qualcomm.com>
Subject: Re: [PATCH v3 3/5] arm64: dts: qcom: Introduce Kaanapali SoC
On 12/11/2025 1:44 PM, Dmitry Baryshkov wrote:
> On Wed, Dec 10, 2025 at 07:05:04PM -0800, Jingyi Wang wrote:
>> Kaanapali is Snapdragon SoC from Qualcomm.
>>
>> Features added in this patch:
>> - CPUs with PSCI idle states and cpufreq
>> - Interrupt-controller with PDC wakeup support
>> - Timers, TCSR Clock Controllers
>> - Reserved Shared memory
>> - GCC and RPMHCC
>> - TLMM
>> - Interconnect with CPU BWMONs
>> - QuP with UART
>> - SMMU
>> - RPMhPD
>> - UFS with Inline Crypto Engine
>> - LLCC
>> - Watchdog
>> - SD Card
>> - PCIe
>>
>> Written with help from Raviteja Laggyshetty (added interconnect nodes),
>> Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash
>> (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE),
>> Manish Pandey (added SD Card) and Qiang Yu (added PCIe).
>>
>> Co-developed-by: Tengfei Fan <tengfei.fan@....qualcomm.com>
>> Signed-off-by: Tengfei Fan <tengfei.fan@....qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1606 +++++++++++++++++++++++++++++++
>> 1 file changed, 1606 insertions(+)
>>
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + pdp_mem: pdp-region@...00000 {
>
> please drop -region, please be consistent
>
>> + reg = <0x0 0x81300000 0x0 0x100000>;
>> + no-map;
>> + };
>> +
>> + aop_cmd_db_mem: aop-cmd-db@...60000 {
>> + compatible = "qcom,cmd-db";
>> + reg = <0x0 0x81c60000 0x0 0x20000>;
>> + no-map;
>> + };
>> +
>> + smem_mem: smem@...00000 {
>> + compatible = "qcom,smem";
>> + reg = <0x0 0x81d00000 0x0 0x200000>;
>> + hwlocks = <&tcsr_mutex 3>;
>> + no-map;
>> + };
>> +
>> + pdp_ns_shared_mem: pdp-ns-shared-region@...00000 {
>
> please drop -region
>
>> + reg = <0x0 0x81f00000 0x0 0x100000>;
>> + no-map;
>> + };
>> +
>
>> +
>> + pcie0: pcie@...0000 {
>> + device_type = "pci";
>> + compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550";
>> + reg = <0 0x01c00000 0 0x3000>,
>
> 0x0 instead of 0 (here and in other reg entries).
>
>> + <0 0x40000000 0 0xf1d>,
>> + <0 0x40000f20 0 0xa8>,
>> + <0 0x40001000 0 0x1000>,
>> + <0 0x40100000 0 0x100000>,
>> + <0 0x01c03000 0 0x1000>;
>> + reg-names = "parf",
>> + "dbi",
>> + "elbi",
>> + "atu",
>> + "config",
>> + "mhi";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
>
> Also 0x0 here
>
thx, will fix these
Thanks,
Jingyi
>> + <0x02000000 0 0x40300000 0 0x40300000 0 0x23d00000>;
>> +
>
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