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Message-Id: <20251216-dt-apm-v1-1-0bf2bf8b982c@kernel.org>
Date: Tue, 16 Dec 2025 14:27:48 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: soc@...nel.org, Khuong Dinh <khuong@...amperecomputing.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 1/4] arm64: dts: apm/shadowcat: More clock clean-ups
A fixed-factor-clock only provides 1 clock, so "#clock-cells" must be 0.
The "snps,designware-i2c" node is not a clock provider, so drop
"#clock-cells.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
---
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 5bbedb0a7107..032d37a32193 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -295,7 +295,7 @@ socpll: socpll@...00120 {
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&socpll 0>;
clock-mult = <1>;
clock-div = <2>;
@@ -305,7 +305,7 @@ socplldiv2: socplldiv2 {
ahbclk: ahbclk@...00000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
@@ -329,7 +329,7 @@ sbapbclk: sbapbclk@...4c000 {
sdioclk: sdioclk@...ac000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
@@ -346,7 +346,7 @@ sdioclk: sdioclk@...ac000 {
pcie0clk: pcie0clk@...bc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2bc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie0clk";
@@ -355,7 +355,7 @@ pcie0clk: pcie0clk@...bc000 {
pcie1clk: pcie1clk@...cc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
@@ -364,7 +364,7 @@ pcie1clk: pcie1clk@...cc000 {
xge0clk: xge0clk@...1c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f61c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
@@ -375,7 +375,7 @@ xge0clk: xge0clk@...1c000 {
xge1clk: xge1clk@...2c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f62c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
@@ -386,7 +386,7 @@ xge1clk: xge1clk@...2c000 {
rngpkaclk: rngpkaclk@...00000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
@@ -799,7 +799,6 @@ i2c1: i2c@...11000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10511000 0x0 0x1000>;
interrupts = <0 0x45 0x4>;
- #clock-cells = <1>;
clocks = <&sbapbclk 0>;
};
--
2.51.0
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