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Message-ID: <20251216220624.GA3114300-robh@kernel.org>
Date: Tue, 16 Dec 2025 16:16:31 -0600
From: Rob Herring <robh@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: linus.walleij@...aro.org, Conor Dooley <conor.dooley@...rochip.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, Valentina.FernandezAlanis@...rochip.com
Subject: Re: [RFC v2 1/5] dt-bindings: pinctrl: document polarfire soc mssio
pin controller
On Thu, Nov 27, 2025 at 10:57:57AM +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the
> Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6,
> which determine what function in routed to them, and
> MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin.
>
> Document it, including several custom configuration options that stem
> from MSS Configurator options (the MSS Configurator is part of the FPGA
> tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping
> with an MSS Configurator option, unlike clamp-diode or lockdown, and I
> do not know the effect of any bits in the field. I have no been able to
> find an explanation for these bits in documentation.
>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 119 ++++++++++++++++++
> .../microchip,mpfs-mss-top-sysreg.yaml | 4 +
> 2 files changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
> new file mode 100644
> index 000000000000..c8e509ba2f51
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Polarfire SoC MSSIO pinctrl
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@...rochip.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: microchip,mpfs-pinctrl-mssio
> + - items:
> + - const: microchip,pic64gx-pinctrl-mssio
> + - const: microchip,mpfs-pinctrl-mssio
> +
> + reg:
> + maxItems: 1
> +
> + pinctrl-use-default: true
> +
> +patternProperties:
> + '-cfg$':
> + type: object
> + additionalProperties: false
> +
> + patternProperties:
> + '-pins$':
> + type: object
> + additionalProperties: false
> +
> + allOf:
> + - $ref: pincfg-node.yaml#
> + - $ref: pinmux-node.yaml#
> +
> + properties:
> + pins:
> + description:
> + The list of IOs that properties in the pincfg node apply to.
pins can be int or string. You need to define which one here.
> +
> + function:
> + description:
> + A string containing the name of the function to mux for these
> + pins. The "reserved" function tristates a pin.
> + enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc
> + reserved, gpio, fabric-test, tied-low, tied-high, tristate ]
> +
> + bias-bus-hold: true
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + input-schmitt-enable: true
> + low-power-enable: true
> +
> + drive-strength:
> + enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ]
> +
> + microchip,bank-voltage-microvolt:
> + description:
> + Which bank voltage to use. This cannot differ for pins in a
> + given bank, the whole bank uses the same voltage.
> + enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ]
"power-source" serves this purpose. It's not well defined as sometimes
it's a register value and sometimes a voltage (in various units).
> +
> + microchip,clamp-diode:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Reflects the "Clamp Diode" setting in the MSS Configurator for
> + this pin. This setting controls whether or not input voltage
> + clamping should be enabled.
> +
> + microchip,ibufmd:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description:
> + Reflects the "IBUFMD" bits in the MSS Configurator output files
> + for this pin.
> +
> + required:
> + - pins
> + - function
> + - microchip,bank-voltage-microvolt
> +
> + if:
> + properties:
> + microchip,bank-voltage-microvolt:
> + contains:
> + enum: [ 1200000, 1500000, 1800000 ]
> + then:
> + required:
> + - input-schmitt-enable
> +
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pinctrl@204 {
> + compatible = "microchip,mpfs-pinctrl-mssio";
> + reg = <0x204 0x7c>;
> +
> + ikrd-spi1-cfg {
> + spi1-pins {
> + pins = <30>, <31>, <32>, <33>;
> + function = "spi";
> + bias-pull-up;
> + drive-strength = <8>;
> + microchip,bank-voltage-microvolt = <3300000>;
> + microchip,ibufmd = <0x1>;
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
> index 39987f722411..44e4a50c3155 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
> @@ -42,6 +42,10 @@ properties:
> type: object
> $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
>
> + pinctrl@204:
> + type: object
> + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
> +
> required:
> - compatible
> - reg
> --
> 2.51.0
>
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