| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20251216064926.15817-6-muhammadamirulasyraf.mohamadjamian@altera.com>
Date: Mon, 15 Dec 2025 22:49:26 -0800
From: muhammadamirulasyraf.mohamadjamian@...era.com
To: Guenter Roeck <linux@...ck-us.net>,
linux-hwmon@...r.kernel.org,
Dinh Nguyen <dinguyen@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Ang Tien Sung <tien.sung.ang@...era.com>,
Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Subject: [PATCH v1 5/5] arm64: dts: socfpga: agilex: Add hwmon node
From: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@...era.com>
The Agilex SoCFPGA platform includes hardware monitoring capabilities that
require proper device tree description.
Currently, the Agilex device tree lacks an hwmon node, preventing the
kernel from binding the corresponding hwmon driver and accessing sensor
data.
This hwmon node with the compatible string "altera,socfpga-hwmon" ensures
the hardware monitoring subsystem can be initialized correctly, enabling
accurate voltage and temperature monitoring.
The node is added for Agilex OOBE Daughter Card, Agilex with NAND daughter
card and N5X.
Define the temperature sensor locations to demonstrate the maximum
temperature value rather than the individual diode values.
- arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
- arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
For N5X, only the main die sensor is present. Also, add Voltage Monitor
labels for the N5X device to align with the descriptions from the N5X
documentation.
- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
Signed-off-by: Ang Tien Sung <tien.sung.ang@...era.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Signed-off-by: Muhammad Amirul Asyraf Mohamad Jamian <muhammad.amirul.asyraf.mohamad.jamian@...era.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_agilex_socdk.dts | 66 +++++++++++++++++++
.../dts/intel/socfpga_agilex_socdk_nand.dts | 66 +++++++++++++++++++
.../boot/dts/intel/socfpga_n5x_socdk.dts | 46 +++++++++++++
5 files changed, 248 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dfbafde8822..0e91a331da69 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -69,6 +69,10 @@ svc {
fpga_mgr: fpga-mgr {
compatible = "intel,agilex-soc-fpga-mgr";
};
+
+ temp_volt: hwmon {
+ compatible = "altr,socfpga-hwmon";
+ };
};
};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index d22de06e9839..f45a76bff82a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -64,3 +64,69 @@ &watchdog0 {
&fpga_mgr {
status = "disabled";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 9ee312bae8d2..33b5286655ef 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -136,3 +136,69 @@ root: partition@...0000 {
};
};
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 98900cb410dc..5246bf8b14b5 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -114,3 +114,69 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VCC";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "1.8V VCCIO_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCPT";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.2V VCCCRCORE";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "0.9V VCCH";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VCCL";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom left max";
+ reg = <0x10000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top left max";
+ reg = <0x20000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner bottom right max";
+ reg = <0x30000>;
+ };
+
+ input@...00 {
+ label = "Main Die corner top right max";
+ reg = <0x40000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 0034a4897220..5ca111c158c4 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -126,3 +126,49 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&temp_volt {
+ voltage {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ input@2 {
+ label = "0.8V VDD";
+ reg = <2>;
+ };
+
+ input@3 {
+ label = "0.8V VDD_SDM";
+ reg = <3>;
+ };
+
+ input@4 {
+ label = "1.8V VCCADC";
+ reg = <4>;
+ };
+
+ input@5 {
+ label = "1.8V VCCPD";
+ reg = <5>;
+ };
+
+ input@6 {
+ label = "1.8V VCCIO_SDM";
+ reg = <6>;
+ };
+
+ input@7 {
+ label = "0.8V VDD_HPS";
+ reg = <7>;
+ };
+ };
+
+ temperature {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ label = "Main Die SDM";
+ reg = <0x0>;
+ };
+ };
+};
--
2.43.7
Powered by blists - more mailing lists