linux-kernel - [PATCH 0/8] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board

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Message-Id: <20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com>
Date: Tue, 16 Dec 2025 21:32:24 +0800
From: Guodong Xu <guodong@...cstar.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <pjw@...nel.org>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>, Yixun Lan <dlan@...too.org>, 
 Daniel Lezcano <daniel.lezcano@...aro.org>, 
 Thomas Gleixner <tglx@...utronix.de>, 
 Samuel Holland <samuel.holland@...ive.com>, 
 Anup Patel <anup@...infault.org>, 
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
 Jiri Slaby <jirislaby@...nel.org>, Lubomir Rintel <lkundrak@...sk>, 
 Yangyu Chen <cyy@...self.name>
Cc: Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>, 
 Heinrich Schuchardt <xypron.glpk@....de>, 
 Kevin Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>, 
 devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, 
 linux-kernel@...r.kernel.org, spacemit@...ts.linux.dev, 
 linux-serial@...r.kernel.org, Guodong Xu <guodong@...cstar.com>
Subject: [PATCH 0/8] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX
 board

This series introduces basic support for the SpacemiT K3 SoC and the
K3 Pico-ITX evaluation board.

The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores.
The X100 is a 4-issue, out-of-order core compliant with the RVA23
profile, targeting high-performance scenarios. [1]

The K3 Pico-ITX is an evaluation board built around the K3 SoC.

This series includes:
 - DT bindings for SpacemiT X100 core, K3 SoC, and Pico-ITX board.
 - DT bindings for K3 integrated peripherals: CLINT, APLIC, IMSIC, and UART.
 - Initial Device Tree for K3 SoC and Pico-ITX board.

>From an RVA23 profile compliance perspective, the X100 supports all
mandatory extensions required by RVA23U64 and RVA23S64. Ideally, all
these extensions should be listed in the 'riscv,isa-extensions' string.
However, some mandatory extensions (e.g. "ziccif", "sstvecd")
are not yet supported (listed) by the upstream riscv/extensions.yaml
binding.

To avoid validation warnings (“Unevaluated properties are not allowed"
when make dtbs_check W=3) and to prevent the kernel from silently
dropping unrecognized strings, this series only declares the
isa-extensions that are currently supported by the kernel bindings.

Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]

Signed-off-by: Guodong Xu <guodong@...cstar.com>
---
Guodong Xu (8):
      dt-bindings: riscv: add SpacemiT X100 CPU compatible
      dt-bindings: timer: add SpacemiT K3 CLINT
      dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
      dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
      dt-bindings: serial: 8250: add SpacemiT K3 UART compatible
      dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
      riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
      riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree

 .../bindings/interrupt-controller/riscv,aplic.yaml |   1 +
 .../interrupt-controller/riscv,imsics.yaml         |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/riscv/spacemit.yaml        |   6 +-
 Documentation/devicetree/bindings/serial/8250.yaml |   1 +
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 arch/riscv/boot/dts/spacemit/Makefile              |   1 +
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts       |  25 +
 arch/riscv/boot/dts/spacemit/k3.dtsi               | 529 +++++++++++++++++++++
 9 files changed, 565 insertions(+), 1 deletion(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20251216-k3-basic-dt-cd9540061989

Best regards,
-- 
Guodong Xu <guodong@...cstar.com>