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Message-Id: <20251217-eyeq6lplus-v1-6-e9cdbd3af4c2@bootlin.com>
Date: Wed, 17 Dec 2025 14:35:56 +0100
From: Benoît Monin <benoit.monin@...tlin.com>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
Gregory CLEMENT <gregory.clement@...tlin.com>,
Théo Lebrun <theo.lebrun@...tlin.com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>,
Linus Walleij <linusw@...nel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>, linux-mips@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
Benoît Monin <benoit.monin@...tlin.com>
Subject: [PATCH 06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin
control is identical in function to the one present in the EyeQ5 but
has a single bank of 32 pins.
Signed-off-by: Benoît Monin <benoit.monin@...tlin.com>
---
drivers/pinctrl/Kconfig | 4 +-
drivers/pinctrl/pinctrl-eyeq5.c | 95 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bc7f37afc48b..c81568d835e6 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -248,11 +248,11 @@ config PINCTRL_EQUILIBRIUM
config PINCTRL_EYEQ5
bool "Mobileye EyeQ5 pinctrl driver"
depends on OF
- depends on MACH_EYEQ5 || COMPILE_TEST
+ depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select AUXILIARY_BUS
- default MACH_EYEQ5
+ default MACH_EYEQ5 || MACH_EYEQ6LPLUS
help
Pin controller driver for the Mobileye EyeQ5 platform. It does both
pin config & pin muxing. It does not handle GPIO.
diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c
index e48add1d965d..729fdf7cbbc2 100644
--- a/drivers/pinctrl/pinctrl-eyeq5.c
+++ b/drivers/pinctrl/pinctrl-eyeq5.c
@@ -229,6 +229,100 @@ static const struct eq5p_match_data eq5p_eyeq5_data = {
.banks = eq5p_eyeq5_banks,
};
+static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = {
+ PINCTRL_PIN(0, "PA0"), /* GPIO_A0_TIMER0_CK0 */
+ PINCTRL_PIN(1, "PA1"), /* GPIO_A1_TIMER0_EOC */
+ PINCTRL_PIN(2, "PA2"), /* GPIO_A2_TIMER1_CK */
+ PINCTRL_PIN(3, "PA3"), /* GPIO_A3_TIMER1_EOC1 */
+ PINCTRL_PIN(4, "PA4"), /* GPIO_A4_SSI_UART_RX */
+ PINCTRL_PIN(5, "PA5"), /* GPIO_A5_SSI_UART_TX */
+ PINCTRL_PIN(6, "PA6"), /* GPIO_A6_SPI_0_CS */
+ PINCTRL_PIN(7, "PA7"), /* GPIO_A7_SPI_0_DI */
+ PINCTRL_PIN(8, "PA8"), /* GPIO_A8_SPI_0_CK */
+ PINCTRL_PIN(9, "PA9"), /* GPIO_A9_SPI_0_DO */
+ PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */
+ PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */
+ PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */
+ PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */
+ PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */
+ PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */
+ PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */
+ PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */
+ PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */
+ PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */
+ PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */
+ PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */
+ PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */
+ PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */
+ PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */
+ PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */
+ PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */
+ PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */
+ PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */
+ PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */
+ PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */
+ PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */
+};
+
+static const char * const eq5p_eyeq6lplus_gpio_groups[] = {
+ /* Bank A */
+ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31",
+};
+
+/* Groups of functions on bank A */
+static const char * const eq5p_eyeq6lplus_timer0_groups[] = { "PA0", "PA1" };
+static const char * const eq5p_eyeq6lplus_timer1_groups[] = { "PA2", "PA3" };
+static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { "PA4", "PA5" };
+static const char * const eq5p_eyeq6lplus_spi0_groups[] = { "PA6", "PA7", "PA8", "PA9", "PA10" };
+static const char * const eq5p_eyeq6lplus_uart0_groups[] = { "PA11", "PA12" };
+static const char * const eq5p_eyeq6lplus_timer2_groups[] = { "PA13", "PA14" };
+static const char * const eq5p_eyeq6lplus_timer3_groups[] = { "PA15", "PA16" };
+static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { "PA17", "PA18", "PA19", "PA20" };
+static const char * const eq5p_eyeq6lplus_spi1_groups[] = {
+ "PA21", "PA22", "PA23", "PA24", "PA25"
+};
+static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { "PA26", "PA27", "PA28", "PA29" };
+static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { "PA30" };
+static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { "PA31" };
+
+static const struct pinfunction eq5p_eyeq6lplus_functions[] = {
+ /* gpios function */
+ EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups),
+
+ /* Bank A alternate functions */
+ EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups),
+ EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups),
+ EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups),
+ EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups),
+ EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups),
+ EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups),
+ EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups),
+ EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups),
+ EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups),
+ EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups),
+ EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups),
+ EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups),
+};
+
+static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = {
+ {
+ .npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
+ .regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
+ },
+};
+
+static const struct eq5p_match_data eq5p_eyeq6lplus_data = {
+ .npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
+ .nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions),
+ .nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks),
+ .pins = eq5p_eyeq6lplus_pins,
+ .functions = eq5p_eyeq6lplus_functions,
+ .banks = eq5p_eyeq6lplus_banks,
+};
+
static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
const struct eq5p_bank *bank,
enum eq5p_regs reg, u32 mask, u32 val)
@@ -666,6 +760,7 @@ static int eq5p_probe(struct auxiliary_device *adev,
static const struct of_device_id eq5p_match_table[] = {
{ .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data },
+ { .compatible = "mobileye,eyeq6lplus-olb", .data = &eq5p_eyeq6lplus_data },
{}
};
MODULE_DEVICE_TABLE(of, eq5p_match_table);
--
2.52.0
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