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Message-ID: <20251217151609.3162665-18-den@valinux.co.jp>
Date: Thu, 18 Dec 2025 00:15:51 +0900
From: Koichiro Den <den@...inux.co.jp>
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Subject: [RFC PATCH v3 17/35] dmaengine: dw-edma: Add helper func to retrieve register base and size
Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA
register block through a memory window.
Add a helper function that returns the physical base and size for a
given DesignWare EP controller.
Signed-off-by: Koichiro Den <den@...inux.co.jp>
---
.../pci/controller/dwc/pcie-designware-ep.c | 1 +
drivers/pci/controller/dwc/pcie-designware.c | 25 +++++++++++++++++++
include/linux/dma/edma.h | 24 ++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 9480aebaa32a..46d18e7945db 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -12,6 +12,7 @@
#include <linux/platform_device.h>
#include "pcie-designware.h"
+#include <linux/dma/edma.h>
#include <linux/pci-epc.h>
#include <linux/pci-epf.h>
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 75fc8b767fcc..1de88df7b1af 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
if (IS_ERR(pci->edma.reg_base))
return PTR_ERR(pci->edma.reg_base);
+ pci->edma.reg_phys = res->start;
+ pci->edma.reg_size = resource_size(res);
} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
+ pci->edma.reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;
+ pci->edma.reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;
}
}
@@ -1204,3 +1208,24 @@ resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
return cpu_phys_addr - reg_addr;
}
+
+int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t *sz)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci;
+
+ if (!ep)
+ return -ENODEV;
+
+ pci = to_dw_pcie_from_ep(ep);
+ if (!pci->edma.reg_base || !pci->edma.reg_phys)
+ return -ENODEV;
+
+ if (phys)
+ *phys = pci->edma.reg_phys;
+ if (sz)
+ *sz = pci->edma.reg_size;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dw_edma_get_reg_window);
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
index 3080747689f6..11d6eeb19fff 100644
--- a/include/linux/dma/edma.h
+++ b/include/linux/dma/edma.h
@@ -11,6 +11,7 @@
#include <linux/device.h>
#include <linux/dmaengine.h>
+#include <linux/pci-epc.h>
#define EDMA_MAX_WR_CH 8
#define EDMA_MAX_RD_CH 8
@@ -60,6 +61,27 @@ enum dw_edma_chip_flags {
DW_EDMA_CHIP_LOCAL = BIT(0),
};
+#if IS_REACHABLE(CONFIG_PCIE_DW)
+/**
+ * dw_edma_get_reg_window - get eDMA register base and size
+ *
+ * @epc: the EPC device with which the eDMA instance is integrated
+ * @phys: the output parameter that returns the register base address
+ * @sz: the output parameter that returns the register space size
+ *
+ * Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA
+ * register block through a memory window. This helper returns the physical
+ * base and size for a given DesignWare EP controller.
+ */
+int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t *sz);
+#else
+static inline int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
+ size_t *sz)
+{
+ return -ENODEV;
+}
+#endif /* CONFIG_PCIE_DW */
+
/**
* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
* @dev: struct device of the eDMA controller
@@ -85,6 +107,8 @@ struct dw_edma_chip {
u32 flags;
void __iomem *reg_base;
+ phys_addr_t reg_phys;
+ size_t reg_size;
u16 ll_wr_cnt;
u16 ll_rd_cnt;
--
2.51.0
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