linux-kernel - Re: [PATCH 1/8] dt-bindings: riscv: add SpacemiT X100 CPU compatible

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Message-ID: <CAH1PCMZ7rA50ns6EFfX2BcouVYX6L+mYkUSYeGjp+fPNLc62gA@mail.gmail.com>
Date: Wed, 17 Dec 2025 11:38:28 +0800
From: Guodong Xu <guodong@...cstar.com>
To: Yixun Lan <dlan@...too.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <pjw@...nel.org>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Alexandre Ghiti <alex@...ti.fr>, Daniel Lezcano <daniel.lezcano@...aro.org>, 
	Thomas Gleixner <tglx@...utronix.de>, Samuel Holland <samuel.holland@...ive.com>, 
	Anup Patel <anup@...infault.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
	Jiri Slaby <jirislaby@...nel.org>, Lubomir Rintel <lkundrak@...sk>, Yangyu Chen <cyy@...self.name>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Conor Dooley <conor@...nel.org>, 
	Heinrich Schuchardt <xypron.glpk@....de>, Kevin Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>, 
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, spacemit@...ts.linux.dev, 
	linux-serial@...r.kernel.org
Subject: Re: [PATCH 1/8] dt-bindings: riscv: add SpacemiT X100 CPU compatible

On Tue, Dec 16, 2025 at 11:16 PM Yixun Lan <dlan@...too.org> wrote:
>
> Hi Guodong,
>
> On 21:32 Tue 16 Dec     , Guodong Xu wrote:
> > Add compatible string for the SpacemiT X100 (RVA23 compliant) core.
> >
> > Link: https://www.spacemit.com/en/spacemit-x100-core/
> it would be better if you can put more description into commit message
> as I don't trust the link too much, it may vanish or change in the future?..

Thanks Yixun for the feedback.
I understand your concerns. I will expand the commit message with more
information about X100 core features so we don't rely solely on the link.

>
> besides, if I remember correctly, there are still few optional
> extensions that not supported by x100, it's worth to list here to
> let community know..

I would prefer not to list the unsupported optional extensions explicitly.
Basically there are two reasons. Since the RISC-V specification includes a
vast number of optional extensions, and they are categorized in four groups
(localized options, develpment options, expansion options, and transitory
options), listing everything not supported would be quite lengthy IMHO.
Secondly, looking at previous commits for other RISC-V CPUs, it doesn't seem
to be the convention to list unsupported extensions.

I will expand the commit message to state X100 supports all _mandatory_
extensions per defined by the RVA23 profile.

I hope this approach is acceptable.

BR,
Guodong

>
> >
> > Signed-off-by: Guodong Xu <guodong@...cstar.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index d733c0bd534fb63ed7c0eada97c42832431f1fc1..cce87092dc7749f49066154d9a256af6c7b6c19f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -62,6 +62,7 @@ properties:
> >                - sifive,u74
> >                - sifive,u74-mc
> >                - spacemit,x60
> > +              - spacemit,x100
> >                - thead,c906
> >                - thead,c908
> >                - thead,c910
> >
> > --
> > 2.43.0
> >
>
> --
> Yixun Lan (dlan)