linux-kernel - Re: [PATCH v3 0/2] soc: qcom: llcc: Add support for Glymur SoC

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Message-ID: <176601285471.201175.3617092991903531436.b4-ty@kernel.org>
Date: Wed, 17 Dec 2025 17:07:36 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>,
	Conor Dooley <conor@...nel.org>,
	Jonathan Cameron <jonathan.cameron@...wei.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	rajendra.nayak@....qualcomm.com,
	sibi.sankar@....qualcomm.com,
	Krzysztof Kozlowski <krzysztof.kozlowski@....qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 0/2] soc: qcom: llcc: Add support for Glymur SoC


On Thu, 11 Dec 2025 14:32:34 +0530, Pankaj Patil wrote:
> Glymur SoC uses the Last Level Cache Controller (LLCC) as its
> system cache controller, update the device-tree bindings to allow
> maximum of 14 registers for llcc block since GLymur has 12 llcc base
> register regions and an additional AND, OR broadcast base register.
> Updated SCT configuration data in the LLCC driver.
> 
> Enabled additional use case IDs defined in
> include/linux/soc/qcom/llcc-qcom.h:
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
      commit: bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60
[2/2] soc: qcom: llcc-qcom: Add support for Glymur
      commit: 0418592550c6a370b2b8a5cbebd53fb7dd63d837

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>