linux-kernel - RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895

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Message-ID: <12a401dc6f0e$441ae1f0$cc50a5d0$@samsung.com>
Date: Wed, 17 Dec 2025 10:03:10 +0530
From: "Alim Akhtar" <alim.akhtar@...sung.com>
To: "'Youngmin Nam'" <youngmin.nam@...sung.com>, <krzk@...nel.org>,
	<s.nawrocki@...sung.com>, <linus.walleij@...aro.org>,
	<peter.griffin@...aro.org>, <semen.protsenko@...aro.org>,
	<ivo.ivanov.ivanov1@...il.com>
Cc: <ryu.real@...sung.com>, <d7271.choe@...sung.com>,
	<shin.son@...sung.com>, <jaewon02.kim@...sung.com>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-samsung-soc@...r.kernel.org>,
	<linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries
 on Exynos2200/7885/8890/8895

Hello Youngmin

> -----Original Message-----
> From: Youngmin Nam <youngmin.nam@...sung.com>
> Sent: Tuesday, December 2, 2025 3:06 PM
> To: krzk@...nel.org; s.nawrocki@...sung.com; alim.akhtar@...sung.com;
> linus.walleij@...aro.org; peter.griffin@...aro.org;
> semen.protsenko@...aro.org; ivo.ivanov.ivanov1@...il.com
> Cc: ryu.real@...sung.com; d7271.choe@...sung.com;
> shin.son@...sung.com; jaewon02.kim@...sung.com; linux-arm-
> kernel@...ts.infradead.org; linux-samsung-soc@...r.kernel.org; linux-
> gpio@...r.kernel.org; linux-kernel@...r.kernel.org; Youngmin Nam
> <youngmin.nam@...sung.com>
> Subject: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on
> Exynos2200/7885/8890/8895
> 
> This patch corrects wrong pin bank table definitions for 4 SoCs based on their
> TRMs.
> 
> Exynos2200
> - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a
>   'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}).
> - Per the SoC TRM these banks must use the 'alive' layout
>   (.fld_width = {4,1,4,4}).
> - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...).
> 
> Exynos7885
> - etc0, etc1: update bank type to match the SoC TRM.
> - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly.
> 
> Exynos8890
> - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as
>   a non-external interrupt bank.
> - gpi1, gpi2: update bank type to match the SoC TRM.
>   exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) ->
>   exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2})
> - Per the SoC TRM, mark etc1 as a non-external interrupt bank.
> - apply lower case style for hex numbers.
> 
> Exynos8895
> - gpa4 is a non-wakeup interrupt bank per the SoC TRM.
>   change EINTW -> EINTN. (The bank_type itself was correct and is kept
>   unchanged.)
> - apply lower case style for hex numbers.
> 
> This aligns the pin-bank tables with the documented bitfield layouts and
> wakeup domains. No DT/ABI change.
> 
> Signed-off-by: Youngmin Nam <youngmin.nam@...sung.com>
> Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>
> Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
> Tested-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>

Tested on Exynosautov920 SADK board

Tested-by: Alim Akhtar <alim.akhtar@...sung.com>