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Message-ID: <20251217055632.1776206-1-adrianhoyin.ng@altera.com>
Date: Wed, 17 Dec 2025 13:56:30 +0800
From: adrianhoyin.ng@...era.com
To: dinguyen@...nel.org,
	mdf@...nel.org,
	yilun.xu@...el.com,
	trix@...hat.com,
	linux-fpga@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com
Subject: [PATCH 0/2] Add Agilex5 SMMU support for service layer and FPGA manager

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

This series adds SMMU support required for reliable FPGA configuration on
Intel Agilex5 SoCs.

On Agilex5, DDR starts at a high physical address and is inaccessible to
the Secure Device Manager (SDM) without SMMU translation. The existing
service layer and FPGA manager drivers do not handle cases where the
SMMU remaps physical addresses to IOVAs, leading to translation faults or
configuration timeouts when SMMU is enabled.

These changes make Agilex5 support SMMU by enabling SMMU-backed buffer
allocation and IOVA remapping in the service layer, and making the FPGA
manager SMMU-aware with DMA mapping and persistent buffer allocation to
avoid repeated IOMMU operations. Together, they ensure robust FPGA
configuration on Agilex5 while maintaining the existing behaviour for
Stratix10 and Agilex7.

Adrian Ng Ho Yin (2):
  firmware: stratix10-svc: Add SMMU support for Agilex5
  fpga: stratix10-soc: Add persistent SMMU-aware DMA handling for
    Agilex5

 drivers/firmware/stratix10-svc.c | 160 ++++++++++++++++++++++++++++---
 drivers/fpga/stratix10-soc.c     |  67 +++++++++----
 2 files changed, 192 insertions(+), 35 deletions(-)

-- 
2.49.GIT


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