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Message-ID: <20251217-sociable-rich-beagle-9321f8@quoll>
Date: Wed, 17 Dec 2025 09:35:44 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Dan Carpenter <dan.carpenter@...aro.org>
Cc: Lee Jones <lee@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, imx@...ts.linux.dev, linaro-s32@...aro.org,
NXP S32 Linux Team <s32@....com>
Subject: Re: [PATCH v2 2/4] dt-bindings: mfd: syscon: Document the GPR syscon
for the NXP S32 SoCs
On Mon, Dec 15, 2025 at 05:41:52PM +0300, Dan Carpenter wrote:
> The NXP S32 SoCs have a GPR region which is used by a variety of
> drivers. Some examples of the registers in this region are:
>
> * DDR_PMU_IRQ
> * GMAC0_PHY_INTF_SEL
> * GMAC1_PHY_INTF_SEL
> * PFE_EMACS_INTF_SEL
> * PFE_COH_EN
> * PFE_PWR_CTRL
> * PFE_EMACS_GENCTRL1
> * PFE_GENCTRL3
>
> Use the syscon interface to access these registers.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
> ---
> v2: Use nxp,s32g2-gpr and nxp,s32g3-gpr instead of nxp,s32g-gpr
>
> Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@....qualcomm.com>
Best regards,
Krzysztof
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