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Message-ID: <20251217102357.1730573-4-wangyushan12@huawei.com>
Date: Wed, 17 Dec 2025 18:23:57 +0800
From: Yushan Wang <wangyushan12@...wei.com>
To: <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<xuwei5@...ilicon.com>, <linuxarm@...wei.com>, <wangzhou1@...ilicon.com>,
<Jonathan.Cameron@...wei.com>
CC: <liuyonglong@...wei.com>, <prime.zeng@...ilicon.com>,
<fanghao11@...wei.com>, <alexandre.belloni@...tlin.com>, <arnd@...db.de>,
<fustini@...nel.org>, <krzk@...nel.org>, <linus.walleij@...aro.org>,
<will@...nel.org>
Subject: [PATCH RFC v2 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache
Add necessary documentation to HiSilicon SoC cache for reference.
Signed-off-by: Yushan Wang <wangyushan12@...wei.com>
---
Documentation/driver-api/hisi-soc-cache.rst | 62 +++++++++++++++++++++
Documentation/driver-api/index.rst | 1 +
MAINTAINERS | 1 +
3 files changed, 64 insertions(+)
create mode 100644 Documentation/driver-api/hisi-soc-cache.rst
diff --git a/Documentation/driver-api/hisi-soc-cache.rst b/Documentation/driver-api/hisi-soc-cache.rst
new file mode 100644
index 000000000000..3c17de79bba2
--- /dev/null
+++ b/Documentation/driver-api/hisi-soc-cache.rst
@@ -0,0 +1,62 @@
+==========================
+HiSilicon SoC Cache Driver
+==========================
+
+Introduction
+============
+
+HiSilicon SoC cache provides the capabilities of preventing given range of
+memory from being evicted from L3 cache. The driver exports the lockdown API to
+userspace, allowing allocation of memory that is guranteed to be placed in L3
+cache, thus decreasing average memory access latency.
+
+Usage
+=====
+
+Kernel built with CONFIG_HISI_SOC_CACHE on will have the device file at
+`/dev/hisi_l3c`, cache operations can be performed through it.
+
+mmap():
+-------
+
+This interface can be used to allocate memory that is guranteed to not be
+evicted out of HiSilicon L3 cache. Newly allocated memory will be prefetched to
+L3 cache automatically.
+
+Users should set `PROT_READ` or `PROT_WRITE` to enable read/write to the memory
+region. Once mmap call succeeds, read and write can be applied to the memory
+region indicated by the returned pointer.
+
+Calling `munmap()` to the pointer can be used to unlock the memory regions.
+
+Restrictions of the cache lockdown are listed below:
+ - Only limited number of memory regions are supported, the exact number is
+ reported by firmware.
+ - Sum of the sizes of locked memory regions should be less than 70% of the
+ total size of cache instance.
+ - Lock/unlock can only be performed during allocation/deallocation, locking
+ existing memory is not supported yet.
+
+ioctl():
+--------
+
+This interface provides useful information of HiSilicon L3 cache.
+
+HISI_L3C_LOCK_INFO
+ - struct hisi_l3c_lock_info (read)
+
+ Gets detailed information of L3 cache lock restrictions.
+
+This ioctl call returns the detailed information of HiSilicon L3 cache lock
+restriction. Information will be presented in the form of::
+
+ struct hisi_l3c_lock_info {
+ unsigned int lock_region_num;
+ size_t lock_size;
+ bool address_alignment;
+ size_t max_lock_size;
+ size_t min_lock_size;
+ };
+
+User may perform a query before issueing cache lock to check for available
+resource.
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index 1833e6a0687e..a1d4bf2a22de 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -95,6 +95,7 @@ Subsystem-specific APIs
generic-counter
generic_pt
gpio/index
+ hisi-soc-cache
hsi
hte/index
hw-recoverable-errors
diff --git a/MAINTAINERS b/MAINTAINERS
index f09b718f59fd..bb79ed1f9d45 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11369,6 +11369,7 @@ F: drivers/soc/hisilicon/kunpeng_hccs.h
HISILICON SOC L3C DRIVER
M: Yushan Wang <wangyushan12@...wei.com>
S: Maintained
+F: Documentation/driver-api/hisi-soc-cache.rst
F: drivers/soc/hisilicon/hisi_soc_l3c.c
F: include/uapi/misc/hisi_l3c.h
--
2.33.0
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