linux-kernel - [tip: perf/core] perf/x86/amd: Support PERF_PMU_CAP_MEDIATED

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Message-ID: <176597508637.510.5295271479609953725.tip-bot2@tip-bot2>
Date: Wed, 17 Dec 2025 12:38:06 -0000
From: "tip-bot2 for Sandipan Das" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Sandipan Das <sandipan.das@....com>, Mingwei Zhang <mizhang@...gle.com>,
 Sean Christopherson <seanjc@...gle.com>,
 "Peter Zijlstra (Intel)" <peterz@...radead.org>,
 Xudong Hao <xudong.hao@...el.com>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for
 AMD host

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     65eb3a9a8a34fa9188e0ab5e657d84ce4fa242a7
Gitweb:        https://git.kernel.org/tip/65eb3a9a8a34fa9188e0ab5e657d84ce4fa242a7
Author:        Sandipan Das <sandipan.das@....com>
AuthorDate:    Fri, 05 Dec 2025 16:16:49 -08:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Wed, 17 Dec 2025 13:31:07 +01:00

perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for AMD host

Apply the PERF_PMU_CAP_MEDIATED_VPMU flag for version 2 and later
implementations of the core PMU. Aside from having Global Control and
Status registers, virtualizing the PMU using the mediated model requires
an interface to set or clear the overflow bits in the Global Status MSRs
while restoring or saving the PMU context of a vCPU.

PerfMonV2-capable hardware has additional MSRs for this purpose, namely
PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it
suitable for use with mediated vPMU.

Signed-off-by: Sandipan Das <sandipan.das@....com>
Signed-off-by: Mingwei Zhang <mizhang@...gle.com>
Signed-off-by: Sean Christopherson <seanjc@...gle.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Tested-by: Xudong Hao <xudong.hao@...el.com>
Link: https://patch.msgid.link/20251206001720.468579-14-seanjc@google.com
---
 arch/x86/events/amd/core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 44656d2..0c92ed5 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1439,6 +1439,8 @@ static int __init amd_core_pmu_init(void)
 
 		amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64;
 
+		x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
+
 		/* Update PMC handling functions */
 		x86_pmu.enable_all = amd_pmu_v2_enable_all;
 		x86_pmu.disable_all = amd_pmu_v2_disable_all;