linux-kernel - Re: [PATCH] Documentation/driver-api/cxl: device hotplug section

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Message-ID: <aUQllpH-4c2pGugv@gourry-fedora-PF4VCD3F>
Date: Thu, 18 Dec 2025 11:02:30 -0500
From: Gregory Price <gourry@...rry.net>
To: Jonathan Cameron <jonathan.cameron@...wei.com>
Cc: linux-cxl@...r.kernel.org, linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org, dave@...olabs.net,
	dave.jiang@...el.com, alison.schofield@...el.com,
	vishal.l.verma@...el.com, ira.weiny@...el.com,
	dan.j.williams@...el.com, corbet@....net, kernel-team@...a.com,
	alejandro.lucero-palau@....com
Subject: Re: [PATCH] Documentation/driver-api/cxl: device hotplug section

On Thu, Dec 18, 2025 at 03:26:16PM +0000, Jonathan Cameron wrote:
> On Thu, 18 Dec 2025 09:46:36 -0500
> Gregory Price <gourry@...rry.net> wrote:
> 
> > Describe cxl memory device hotplug implications, in particular how the
> > platform CEDT CFMWS must be described to support successful hot-add of
> > memory devices.
> > 
> > Signed-off-by: Gregory Price <gourry@...rry.net>
> 
> Hi Gregory,
> 
> Thanks for drawing this up.

ack on most of your notes, discussion on platform/switch stuff

> > +CEDT CFMWS region with sufficient memory capacity to cover all future
> > +potentially added capacity.
> > +
> > +Switches in the fabric should report the max possible memory capacity
> > +expected to be hot-added so that platform software may construct the
> > +appropriately sized CFMWS.
> 
> How do switches report this? I don't think they can as it really has nothing
> to do with the switch beyond maybe how many DSPs it has (which incidentally
> is what is used to work out space for PCI HP where the code divides up space
> left over space between HP DSPs.).
> 
> Obviously this excludes the weird switches that are out there than pretend
> to be a single memory device as those are not switches at all as far
> as Linux is concerned.
> 

Good point - in reality, it probably should say something like:

```
A hot-plug capable CXL memory device should report the maximum possible
capacity for the device in the CEDT CFMWS, rather than the CFMWS memory
region to the capacity present at boot time.

To support memory device hotplug directly on the host bridge (or on a
switch downstream of a HB without built-in memory device capabilities),
a platform must construct a CEDT CFMWS at boot with sufficient resources
to support the max possible (or expected) hotplug memory capacity.
```

In one case, an attached device which supports hotplug (which somewhat
implies a switch is present), is responsible for presenting the platform
the resources.  In theory, at least, a platform doesn't need to do
anything here if the device vendor has set things up correctly.

In the second case, the platform is responsible for making that decision,
at it's on the ODM+CPU manufacturers to make sufficient BIOS/EFI/etc
options available to support this kind of pre-allocation lacking any
attached device at boot.  (not sure whether i should add this explicitly
above).

> > +Platform vendors should work with switch vendors to work out how this
> > +HPA space reservation should work when one or more interleave options are
> > +intended to be presented to a host.
> 
> Same as above. Nothing to do with switches as far as I understand things
> beyond them providing fan out. So if you have
>        HB0          HB1
>     RP0 RP1         RP2
>      |   |           | 
>    Empty Empty      USP
>               _______|_______
>              |    |   |     |
>             DSP  DSP  DSP   DSP
>              |    |   |     |
>                 All empty
> 
> You might provide more room for devices below HB1 than HB0 if you don't expect
> to see switches being hot added.
> 

Same note from above

also *yoink* your ascii :]

~Gregory