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Message-ID: <80809872-fb67-6568-7362-d92dcdc9f76b@amd.com>
Date: Thu, 18 Dec 2025 10:42:23 -0800
From: Lizhi Hou <lizhi.hou@....com>
To: Mario Limonciello <superm1@...nel.org>, <ogabbay@...nel.org>,
<quic_jhugo@...cinc.com>, <dri-devel@...ts.freedesktop.org>,
<maciej.falkowski@...ux.intel.com>
CC: <linux-kernel@...r.kernel.org>, <max.zhen@....com>, <sonal.santan@....com>
Subject: Re: [PATCH V1] accel/amdxdna: Remove NPU2 support
Applied to drm-misc-next
On 12/17/25 11:13, Mario Limonciello wrote:
> On 12/17/25 1:08 PM, Lizhi Hou wrote:
>> NPU2 hardware was never publicly released and is now obsolete.
>> Remove all remaining NPU2 support from the driver.
>>
>> Signed-off-by: Lizhi Hou <lizhi.hou@....com>
> Reviewed-by: Mario Limonciello (AMD) <superm1@...nel.org>> ---
>> drivers/accel/amdxdna/Makefile | 1 -
>> drivers/accel/amdxdna/amdxdna_pci_drv.c | 1 -
>> drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 -
>> drivers/accel/amdxdna/npu2_regs.c | 117 ------------------------
>> 4 files changed, 120 deletions(-)
>> delete mode 100644 drivers/accel/amdxdna/npu2_regs.c
>>
>> diff --git a/drivers/accel/amdxdna/Makefile
>> b/drivers/accel/amdxdna/Makefile
>> index 6344aaf523fa..3fa0e74fd8f5 100644
>> --- a/drivers/accel/amdxdna/Makefile
>> +++ b/drivers/accel/amdxdna/Makefile
>> @@ -18,7 +18,6 @@ amdxdna-y := \
>> amdxdna_sysfs.o \
>> amdxdna_ubuf.o \
>> npu1_regs.o \
>> - npu2_regs.o \
>> npu4_regs.o \
>> npu5_regs.o \
>> npu6_regs.o
>> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c
>> b/drivers/accel/amdxdna/amdxdna_pci_drv.c
>> index fcf7e7869007..7d59764d7869 100644
>> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
>> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
>> @@ -51,7 +51,6 @@ MODULE_DEVICE_TABLE(pci, pci_ids);
>> static const struct amdxdna_device_id amdxdna_ids[] = {
>> { 0x1502, 0x0, &dev_npu1_info },
>> - { 0x17f0, 0x0, &dev_npu2_info },
>> { 0x17f0, 0x10, &dev_npu4_info },
>> { 0x17f0, 0x11, &dev_npu5_info },
>> { 0x17f0, 0x20, &dev_npu6_info },
>> diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h
>> b/drivers/accel/amdxdna/amdxdna_pci_drv.h
>> index 0d50c4c8b353..6580cb5ec7e2 100644
>> --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
>> +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
>> @@ -137,7 +137,6 @@ struct amdxdna_client {
>> /* Add device info below */
>> extern const struct amdxdna_dev_info dev_npu1_info;
>> -extern const struct amdxdna_dev_info dev_npu2_info;
>> extern const struct amdxdna_dev_info dev_npu4_info;
>> extern const struct amdxdna_dev_info dev_npu5_info;
>> extern const struct amdxdna_dev_info dev_npu6_info;
>> diff --git a/drivers/accel/amdxdna/npu2_regs.c
>> b/drivers/accel/amdxdna/npu2_regs.c
>> deleted file mode 100644
>> index ad0743fb06d5..000000000000
>> --- a/drivers/accel/amdxdna/npu2_regs.c
>> +++ /dev/null
>> @@ -1,117 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0
>> -/*
>> - * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
>> - */
>> -
>> -#include <drm/amdxdna_accel.h>
>> -#include <drm/drm_device.h>
>> -#include <drm/gpu_scheduler.h>
>> -#include <linux/sizes.h>
>> -
>> -#include "aie2_pci.h"
>> -#include "amdxdna_mailbox.h"
>> -#include "amdxdna_pci_drv.h"
>> -
>> -/* NPU Public Registers on MpNPUAxiXbar (refer to Diag
>> npu_registers.h) */
>> -#define MPNPU_PWAITMODE 0x301003C
>> -#define MPNPU_PUB_SEC_INTR 0x3010060
>> -#define MPNPU_PUB_PWRMGMT_INTR 0x3010064
>> -#define MPNPU_PUB_SCRATCH0 0x301006C
>> -#define MPNPU_PUB_SCRATCH1 0x3010070
>> -#define MPNPU_PUB_SCRATCH2 0x3010074
>> -#define MPNPU_PUB_SCRATCH3 0x3010078
>> -#define MPNPU_PUB_SCRATCH4 0x301007C
>> -#define MPNPU_PUB_SCRATCH5 0x3010080
>> -#define MPNPU_PUB_SCRATCH6 0x3010084
>> -#define MPNPU_PUB_SCRATCH7 0x3010088
>> -#define MPNPU_PUB_SCRATCH8 0x301008C
>> -#define MPNPU_PUB_SCRATCH9 0x3010090
>> -#define MPNPU_PUB_SCRATCH10 0x3010094
>> -#define MPNPU_PUB_SCRATCH11 0x3010098
>> -#define MPNPU_PUB_SCRATCH12 0x301009C
>> -#define MPNPU_PUB_SCRATCH13 0x30100A0
>> -#define MPNPU_PUB_SCRATCH14 0x30100A4
>> -#define MPNPU_PUB_SCRATCH15 0x30100A8
>> -#define MP0_C2PMSG_73 0x3810A24
>> -#define MP0_C2PMSG_123 0x3810AEC
>> -
>> -#define MP1_C2PMSG_0 0x3B10900
>> -#define MP1_C2PMSG_60 0x3B109F0
>> -#define MP1_C2PMSG_61 0x3B109F4
>> -
>> -#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000
>> -#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000
>> -#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000
>> -#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000
>> -
>> -#define MMNPU_APERTURE0_BASE 0x3000000
>> -#define MMNPU_APERTURE1_BASE 0x3600000
>> -#define MMNPU_APERTURE3_BASE 0x3810000
>> -#define MMNPU_APERTURE4_BASE 0x3B10000
>> -
>> -/* PCIe BAR Index for NPU2 */
>> -#define NPU2_REG_BAR_INDEX 0
>> -#define NPU2_MBOX_BAR_INDEX 0
>> -#define NPU2_PSP_BAR_INDEX 4
>> -#define NPU2_SMU_BAR_INDEX 5
>> -#define NPU2_SRAM_BAR_INDEX 2
>> -/* Associated BARs and Apertures */
>> -#define NPU2_REG_BAR_BASE MMNPU_APERTURE0_BASE
>> -#define NPU2_MBOX_BAR_BASE MMNPU_APERTURE0_BASE
>> -#define NPU2_PSP_BAR_BASE MMNPU_APERTURE3_BASE
>> -#define NPU2_SMU_BAR_BASE MMNPU_APERTURE4_BASE
>> -#define NPU2_SRAM_BAR_BASE MMNPU_APERTURE1_BASE
>> -
>> -static const struct amdxdna_dev_priv npu2_dev_priv = {
>> - .fw_path = "amdnpu/17f0_00/npu.sbin",
>> - .protocol_major = 0x6,
>> - .protocol_minor = 0x6,
>> - .rt_config = npu4_default_rt_cfg,
>> - .dpm_clk_tbl = npu4_dpm_clk_table,
>> - .fw_feature_tbl = npu4_fw_feature_table,
>> - .col_align = COL_ALIGN_NATURE,
>> - .mbox_dev_addr = NPU2_MBOX_BAR_BASE,
>> - .mbox_size = 0, /* Use BAR size */
>> - .sram_dev_addr = NPU2_SRAM_BAR_BASE,
>> - .hwctx_limit = 16,
>> - .sram_offs = {
>> - DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM,
>> MPNPU_SRAM_X2I_MAILBOX_0),
>> - DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU2_SRAM,
>> MPNPU_SRAM_X2I_MAILBOX_15),
>> - },
>> - .psp_regs_off = {
>> - DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU2_PSP, MP0_C2PMSG_123),
>> - DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU2_REG,
>> MPNPU_PUB_SCRATCH3),
>> - DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU2_REG,
>> MPNPU_PUB_SCRATCH4),
>> - DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU2_REG,
>> MPNPU_PUB_SCRATCH9),
>> - DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU2_PSP, MP0_C2PMSG_73),
>> - DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),
>> - DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU2_REG,
>> MPNPU_PUB_SCRATCH3),
>> - DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU2_REG,
>> MPNPU_PWAITMODE),
>> - },
>> - .smu_regs_off = {
>> - DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU2_SMU, MP1_C2PMSG_0),
>> - DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU2_SMU, MP1_C2PMSG_60),
>> - DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU,
>> MMNPU_APERTURE4_BASE),
>> - DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61),
>> - DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU2_SMU, MP1_C2PMSG_60),
>> - },
>> - .hw_ops = {
>> - .set_dpm = npu4_set_dpm,
>> - },
>> -};
>> -
>> -const struct amdxdna_dev_info dev_npu2_info = {
>> - .reg_bar = NPU2_REG_BAR_INDEX,
>> - .mbox_bar = NPU2_MBOX_BAR_INDEX,
>> - .sram_bar = NPU2_SRAM_BAR_INDEX,
>> - .psp_bar = NPU2_PSP_BAR_INDEX,
>> - .smu_bar = NPU2_SMU_BAR_INDEX,
>> - .first_col = 0,
>> - .dev_mem_buf_shift = 15, /* 32 KiB aligned */
>> - .dev_mem_base = AIE2_DEVM_BASE,
>> - .dev_mem_size = AIE2_DEVM_SIZE,
>> - .vbnv = "RyzenAI-npu2",
>> - .device_type = AMDXDNA_DEV_TYPE_KMQ,
>> - .dev_priv = &npu2_dev_priv,
>> - .ops = &aie2_ops, /* NPU2 can share NPU1's
>> callback */
>> -};
>
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