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Message-ID: <CAA+D8AMd-4qwYEBQ-JC1D88MRCj9ogeVspN+w-87P8-MWP4FmA@mail.gmail.com>
Date: Thu, 18 Dec 2025 14:55:20 +0800
From: Shengjiu Wang <shengjiu.wang@...il.com>
To: Alexander Stein <alexander.stein@...tq-group.com>
Cc: Xiubo Li <Xiubo.Lee@...il.com>, Fabio Estevam <festevam@...il.com>, 
	Nicolin Chen <nicoleotsuka@...il.com>, Liam Girdwood <lgirdwood@...il.com>, 
	Mark Brown <broonie@...nel.org>, Jaroslav Kysela <perex@...ex.cz>, Takashi Iwai <tiwai@...e.com>, 
	linux-sound@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] ASoC: fsl_xcvr: provide regmap names

On Tue, Dec 16, 2025 at 4:50 PM Alexander Stein
<alexander.stein@...tq-group.com> wrote:
>
> This driver uses multiple regmaps, which will causes name conflicts
> in debugfs like:
>   debugfs: '30cc0000.xcvr' already exists in 'regmap'
> Fix this by adding a name for the non-core regmap configurations.
>
> Signed-off-by: Alexander Stein <alexander.stein@...tq-group.com>

Reviewed-by: Shengjiu Wang <shengjiu.wang@...il.com>

Best regards
Shengjiu Wang
> ---
>  sound/soc/fsl/fsl_xcvr.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
> index 06434b2c9a0fb..a268fb81a2f86 100644
> --- a/sound/soc/fsl/fsl_xcvr.c
> +++ b/sound/soc/fsl/fsl_xcvr.c
> @@ -1323,6 +1323,7 @@ static const struct reg_default fsl_xcvr_phy_reg_defaults[] = {
>  };
>
>  static const struct regmap_config fsl_xcvr_regmap_phy_cfg = {
> +       .name = "phy",
>         .reg_bits = 8,
>         .reg_stride = 4,
>         .val_bits = 32,
> @@ -1335,6 +1336,7 @@ static const struct regmap_config fsl_xcvr_regmap_phy_cfg = {
>  };
>
>  static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = {
> +       .name = "pllv0",
>         .reg_bits = 8,
>         .reg_stride = 4,
>         .val_bits = 32,
> @@ -1345,6 +1347,7 @@ static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = {
>  };
>
>  static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = {
> +       .name = "pllv1",
>         .reg_bits = 8,
>         .reg_stride = 4,
>         .val_bits = 32,
> --
> 2.43.0
>

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