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Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-12-8ad505173e44@bootlin.com>
Date: Fri, 19 Dec 2025 20:22:14 +0100
From: "Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
To: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>, Vaishnav Achath <vaishnav.a@...com>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Hervé Codina <herve.codina@...tlin.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Vignesh Raghavendra <vigneshr@...com>, Santhosh Kumar K <s-k6@...com>,
Pratyush Yadav <pratyush@...nel.org>,
Pascal Eberhard <pascal.eberhard@...com>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
"Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
Subject: [PATCH 12/13] spi: cadence-qspi: Add support for the Renesas RZ/N1
controller
Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence
IP with the following settings:
- a limited bus clock range
- no DTR support
- no DMA
- no useful interrupt flag
- only direct accesses (no INDAC mode)
- write protection
The controller has been tested by running the SPI NOR check list with a
custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad
SPI.
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@...tlin.com>
---
Output of the SPI NOR test procedure:
s25fl128s1
0120184d0180
spansion
xxd: /sys/bus/spi/devices/spi0.0/spi-nor/sfdp: No such file or directory
md5sum: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/sfdp': No such file or directory
1+0 records in
1+0 records out
Copied 65536 bytes from qspi_test to address 0x00000000 in flash
Erased 65536 bytes from address 0x00000000 in flash
Copied 65536 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0010000
Copied 65536 bytes from qspi_test to address 0x00000000 in flash
Copied 65536 bytes from address 0x00000000 in flash to qspi_read
71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_test
71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_read
Read speed:
* page read speed is 6464 KiB/s
* 2 page read speed is 9014 KiB/s
* eraseblock read speed is 14222 KiB/s
Write speed:
* page write speed is 621 KiB/s
* 2 page write speed is 626 KiB/s
* eraseblock write speed is 633 KiB/s
Erase speed:
* erase speed is 617 KiB/s
---
drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index ef036a65c628..03963857664b 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -110,6 +110,7 @@ struct cqspi_st {
bool apb_ahb_hazard;
bool is_jh7110; /* Flag for StarFive JH7110 SoC */
+ bool is_rzn1; /* Flag for Renesas RZN1 SoC */
bool disable_stig_mode;
refcount_t refcount;
refcount_t inflight_ops;
@@ -1343,8 +1344,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
* mode. So, we can not use direct mode when in DTR mode for writing
* data.
*/
- if (!op->cmd.dtr && cqspi->use_direct_mode &&
- cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
+ if ((!op->cmd.dtr && cqspi->use_direct_mode &&
+ cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) ||
+ (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {
memcpy_toio(cqspi->ahb_base + to, buf, len);
return cqspi_wait_idle(cqspi);
}
@@ -1518,6 +1520,7 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
static bool cqspi_supports_mem_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
+ struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
bool all_true, all_false;
/*
@@ -1544,6 +1547,9 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem,
/* A single opcode is supported, it will be repeated */
if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF))
return false;
+
+ if (cqspi->is_rzn1)
+ return false;
} else if (!all_false) {
/* Mixed DTR modes are not supported. */
return false;
@@ -1804,6 +1810,8 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi = spi_controller_get_devdata(host);
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
cqspi->is_jh7110 = true;
+ if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi"))
+ cqspi->is_rzn1 = true;
cqspi->pdev = pdev;
cqspi->host = host;
@@ -1898,7 +1906,12 @@ static int cqspi_probe(struct platform_device *pdev)
reset_control_deassert(rstc_ocp);
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk);
- host->max_speed_hz = cqspi->master_ref_clk_hz;
+ if (!cqspi->is_rzn1) {
+ host->max_speed_hz = cqspi->master_ref_clk_hz;
+ } else {
+ host->max_speed_hz = cqspi->master_ref_clk_hz / 2;
+ host->min_speed_hz = cqspi->master_ref_clk_hz / 32;
+ }
/* write completion is supported by default */
cqspi->wr_completion = true;
@@ -1969,7 +1982,7 @@ static int cqspi_probe(struct platform_device *pdev)
if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET))
cqspi_device_reset(cqspi);
- if (cqspi->use_direct_mode) {
+ if (cqspi->use_direct_mode && !cqspi->is_rzn1) {
ret = cqspi_request_mmap_dma(cqspi);
if (ret == -EPROBE_DEFER)
goto disable_controller;
@@ -2148,6 +2161,12 @@ static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
CQSPI_RD_NO_IRQ,
};
+static const struct cqspi_driver_platdata renesas_rzn1_qspi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_QUAD,
+ .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ |
+ CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -2189,6 +2208,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "amd,versal2-ospi",
.data = &versal2_ospi,
},
+ {
+ .compatible = "renesas,rzn1-qspi",
+ .data = &renesas_rzn1_qspi,
+ },
{ /* end of table */ }
};
--
2.51.1
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