| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <aUT3XYQmn51tLItg@duge-virtual-machine>
Date: Fri, 19 Dec 2025 14:57:33 +0800
From: Jiayu Du <jiayu.riscv@...c.iscas.ac.cn>
To: Xukai Wang <kingxukai@...omail.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Samuel Holland <samuel.holland@...ive.com>,
Troy Mitchell <TroyMitchell988@...il.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v9 0/3] riscv: canaan: Add support for K230 clock
I'm writing to share test results and the corresponding patch for
K230 clock configuration issues, covering critical clock flag
settings and HS/SD subsystem clock adjustments.
1. Critical Clock Protection for CPU Subsystems
I found that cpu0/cpu1 core-related clocks (src/plic/apb/noc_ddrcp4
etc.) had no protection, risking accidental disabling and subsystem
malfunctions. I added the `CLK_IS_CRITICAL` flag to these clock
nodes to block unintended disable operations.
2. HS/SD Clock Setting Fixes
Two hardware-spec mismatches were fixed:
- Adjusted `hs_hclk_src_gate` from register bit1 to bit0, and
updated its parent clock from `hs_hclk_high_src_rate` to
`hs_hclk_high_gate`.
- Corrected `hs_sd_card_src_rate` parent clock from `pll0_div4` to
`hs_sd_card_src_gate`, fixing SD controller clock source
misconfiguration.
3. Test Verification
Post-fix on-board testing confirmed all modified clock nodes align
with K230 hardware specs and the clock tree relationships are
correct.
The CPU core and HS/SD subsystems run stably without any clock-
related errors or anomalies.
The patch modifies `drivers/clk/clk-k230.c` (19 insertions, 19
deletions), with the full diff attached below for your review.
Best regards,
Jiayu Du
---
drivers/clk/clk-k230.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/clk-k230.c b/drivers/clk/clk-k230.c
index 8750e9cbac..43a4e61a0c 100644
--- a/drivers/clk/clk-k230.c
+++ b/drivers/clk/clk-k230.c
@@ -317,7 +317,7 @@ struct clk_fixed_factor *k230_pll_divs[] = {
K230_CLK_GATE_FORMAT(cpu0_src_gate,
K230_CPU0_SRC_GATE,
- 0, 0, 0, 0,
+ 0, 0, CLK_IS_CRITICAL, 0,
&pll0_div2.hw);
K230_CLK_RATE_FORMAT(cpu0_src_rate,
@@ -325,7 +325,7 @@ K230_CLK_RATE_FORMAT(cpu0_src_rate,
1, 16, 1, 0xF,
16, 16, 0, 0x0,
0x0, 31, mul, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_src_gate.clk.hw);
K230_CLK_RATE_FORMAT(cpu0_axi_rate,
@@ -333,12 +333,12 @@ K230_CLK_RATE_FORMAT(cpu0_axi_rate,
1, 1, 0, 0,
1, 8, 6, 0x7,
0x0, 31, div, 0x0,
- 0, 0,
+ 0, CLK_IS_CRITICAL,
&cpu0_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_plic_gate,
K230_CPU0_PLIC_GATE,
- 0x0, 9, 0, 0,
+ 0x0, 9, CLK_IS_CRITICAL, 0,
&cpu0_src_rate.clk.hw);
K230_CLK_RATE_FORMAT(cpu0_plic_rate,
@@ -346,17 +346,17 @@ K230_CLK_RATE_FORMAT(cpu0_plic_rate,
1, 1, 0, 0,
1, 8, 10, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_plic_gate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_noc_ddrcp4_gate,
K230_CPU0_NOC_DDRCP4_GATE,
- 0x60, 7, 0, 0,
+ 0x60, 7, CLK_IS_CRITICAL, 0,
&cpu0_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_apb_gate,
K230_CPU0_APB_GATE,
- 0x0, 13, 0, 0,
+ 0x0, 13, CLK_IS_CRITICAL, 0,
&pll0_div4.hw);
K230_CLK_RATE_FORMAT(cpu0_apb_rate,
@@ -364,7 +364,7 @@ K230_CLK_RATE_FORMAT(cpu0_apb_rate,
1, 1, 0, 0,
1, 8, 15, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_apb_gate.clk.hw);
static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
@@ -376,12 +376,12 @@ static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
K230_CLK_MUX_FORMAT(cpu1_src_mux,
K230_CPU1_SRC_MUX,
0x4, 1, 0x3,
- 0, 0,
+ CLK_IS_CRITICAL, 0,
k230_cpu1_src_mux_pdata);
K230_CLK_GATE_FORMAT(cpu1_src_gate,
K230_CPU1_SRC_GATE,
- 0x4, 0, CLK_IGNORE_UNUSED, 0,
+ 0x4, 0, CLK_IS_CRITICAL, 0,
&cpu1_src_mux.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_src_rate,
@@ -389,7 +389,7 @@ K230_CLK_RATE_FORMAT(cpu1_src_rate,
1, 1, 0, 0,
1, 8, 3, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_src_gate.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_axi_rate,
@@ -397,12 +397,12 @@ K230_CLK_RATE_FORMAT(cpu1_axi_rate,
1, 1, 0, 0,
1, 8, 12, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu1_plic_gate,
K230_CPU1_PLIC_GATE,
- 0x4, 15, CLK_IGNORE_UNUSED, 0,
+ 0x4, 15, CLK_IS_CRITICAL, 0,
&cpu1_src_rate.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_plic_rate,
@@ -410,12 +410,12 @@ K230_CLK_RATE_FORMAT(cpu1_plic_rate,
1, 1, 0, 0,
1, 8, 16, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_plic_gate.clk.hw);
K230_CLK_GATE_FORMAT(cpu1_apb_gate,
K230_CPU1_APB_GATE,
- 0x4, 19, 0, 0,
+ 0x4, 19, CLK_IS_CRITICAL, 0,
&pll0_div4.hw);
K230_CLK_RATE_FORMAT(cpu1_apb_rate,
@@ -423,7 +423,7 @@ K230_CLK_RATE_FORMAT(cpu1_apb_rate,
1, 1, 0, 0,
1, 8, 15, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_apb_gate.clk.hw);
K230_CLK_GATE_FORMAT_PNAME(pmu_apb_gate,
@@ -446,8 +446,8 @@ K230_CLK_GATE_FORMAT(hs_hclk_high_gate,
K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
K230_HS_HCLK_SRC_GATE,
- 0x18, 1, 0, 0,
- &hs_hclk_high_src_rate.clk.hw);
+ 0x18, 0, 0, 0,
+ &hs_hclk_high_gate.clk.hw);
K230_CLK_RATE_FORMAT(hs_hclk_src_rate,
K230_HS_HCLK_SRC_RATE,
@@ -560,7 +560,7 @@ K230_CLK_RATE_FORMAT(hs_sd_card_src_rate,
2, 8, 12, 0x7,
0x1C, 31, div, 0x0,
false, 0,
- &pll0_div4.hw);
+ &hs_sd_card_src_gate.clk.hw);
K230_CLK_GATE_FORMAT(hs_sd0_card_gate,
K230_HS_SD0_CARD_GATE,
Powered by blists - more mailing lists