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Message-ID: <b09d427d-0276-46ef-ac85-8f4bd4dbf42e@oss.qualcomm.com>
Date: Fri, 19 Dec 2025 13:32:25 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Harshal Dev <harshal.dev@....qualcomm.com>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-crypto@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Wenjia Zhang <wenjia.zhang@....qualcomm.com>
Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: x1e80100: add TRNG node
On 12/11/25 9:45 AM, Harshal Dev wrote:
> The x1e80100 SoC has a True Random Number Generator, add the node with
> the correct compatible set.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> Tested-by: Wenjia Zhang <wenjia.zhang@....qualcomm.com>
> Signed-off-by: Harshal Dev <harshal.dev@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 51576d9c935d..c17c02c347be 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3033,6 +3033,11 @@ usb_1_ss2_qmpphy_dp_in: endpoint {
> };
> };
>
> + rng: rng@...3000 {
> + compatible = "qcom,x1e80100-trng", "qcom,trng";
> + reg = <0x0 0x10c3000 0x0 0x1000>;
Please add a leading zero to the address, so that it's padded to 8
hex digits, like all other nodes in this file
with that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Konrad
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