linux-kernel - Re: [PATCH 13/13] ARM: dts: r9a06g032: Describe the QSPI controller

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Message-ID: <20251220-shapeless-mussel-of-temperance-2c4874@quoll>
Date: Sat, 20 Dec 2025 10:36:46 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: "Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
Cc: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, 
	Vaishnav Achath <vaishnav.a@...com>, Thomas Petazzoni <thomas.petazzoni@...tlin.com>, 
	Hervé Codina <herve.codina@...tlin.com>, Wolfram Sang <wsa+renesas@...g-engineering.com>, 
	Vignesh Raghavendra <vigneshr@...com>, Santhosh Kumar K <s-k6@...com>, 
	Pratyush Yadav <pratyush@...nel.org>, Pascal Eberhard <pascal.eberhard@...com>, 
	linux-spi@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH 13/13] ARM: dts: r9a06g032: Describe the QSPI controller

On Fri, Dec 19, 2025 at 08:22:15PM +0100, Miquel Raynal (Schneider Electric) wrote:
> Add a node describing the QSPI controller.
> There are 2 clocks feeding this controller:
> - one for the reference clock
> - one that feeds both the ahb and the apb interfaces
> As the binding expect either the ref clock, or all three (ref, ahb and
> apb) clocks, it makes sense to provide the same clock twice.
> 
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@...tlin.com>
> ---
>  arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> index 8debb77803bb..a6f4670f5c45 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> @@ -66,6 +66,20 @@ soc {
>  		#size-cells = <1>;
>  		ranges;
>  
> +		qspi0: spi@...05000 {
> +			compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;

reg is always the second property.

> +			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> +				 <&sysctrl R9A06G032_HCLK_QSPI0>;
> +			clock-names = "ref", "ahb", "apb";
> +			cdns,fifo-width = <4>;
> +			cdns,trigger-address = <0>;
> +			status = "disabled";
> +		};
> +
>  		rtc0: rtc@...06000 {
>  			compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
>  			reg = <0x40006000 0x1000>;

Even nodes around tend to agree...

Best regards,
Krzysztof