linux-kernel - Re: [PATCH v8 2/3] clock: eswin: Add eic7700 clock driver

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Message-ID: <aUYXPBFhqz3Frdmo@troy-wujie14pro-arch>
Date: Sat, 20 Dec 2025 11:25:48 +0800
From: Troy Mitchell <troy.mitchell@...ux.dev>
To: Bo Gan <ganboing@...il.com>, Troy Mitchell <troy.mitchell@...ux.dev>,
	dongxuyang@...incomputing.com, mturquette@...libre.com,
	sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	bmasney@...hat.com
Cc: ningyu@...incomputing.com, linmin@...incomputing.com,
	huangyifeng@...incomputing.com, pinkesh.vaghela@...fochips.com
Subject: Re: [PATCH v8 2/3] clock: eswin: Add eic7700 clock driver

On Fri, Dec 19, 2025 at 02:39:41PM -0800, Bo Gan wrote:
> Hi ESWIN folks,
> 
> Please refer to my comments below
> 
> On 12/18/25 18:50, Troy Mitchell wrote:
> > Hi Xuyang,
> > This is a quick review.
> > 
> > On Thu, Nov 13, 2025 at 09:38:46AM +0800, dongxuyang@...incomputing.com wrote:
> > > From: Xuyang Dong <dongxuyang@...incomputing.com>
> > > 
> 
> ...
> 
> > > +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > > +			    unsigned long parent_rate)
> > > +{
> > > +	struct eswin_clk_pll *clk = to_pll_clk(hw);
> > > +	struct clk *clk_cpu_lp_pll = NULL;
> > > +	struct clk *clk_cpu_mux = NULL;
> > > +	struct clk *clk_cpu_pll = NULL;
> > > +	u32 postdiv1_val = 0, refdiv_val = 1;
> > > +	u32 frac_val, fbdiv_val, val;
> > > +	bool lock_flag = false;
> > > +	int try_count = 0;
> > > +	int ret;
> > > +
> > > +	ret = eswin_calc_pll(&frac_val,  &fbdiv_val, (u64)rate, clk);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	/* Must switch the CPU to other CLK before we change the CPU PLL. */
> > > +	if (clk->id == EIC7700_CLK_PLL_CPU) {
> > > +		clk_cpu_mux = __clk_lookup("mux_cpu_root_3mux1_gfree");
> > It seems you want to switch to a safe clock source before setting up the
> > PLL, right?
> > 
> > I am not sure whether your approach is correct, but the use of
> > __clk_lookup() should be avoided whenever possible.
> > Would it be feasible to obtain a proper clock handle somewhere and
> > perform the necessary configuration from within a clk_notifier instead?
> > > +		if (!clk_cpu_mux) {
> > > +			pr_err("failed to get clk: %s\n",
> > > +			       "mux_cpu_root_3mux1_gfree");
> > > +			return -EINVAL;
> > > +		}
> 
> I have a strong feeling that this switch to safe clock and back to PLL
> can be done with something very similar to this:
> 
> "Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC"
> https://lore.kernel.org/all/20240826080430.179788-1-xingyu.wu@starfivetech.com/
> 
YES, That's what I want.
Thanks for your link!

                    - Troy
> Please take a look. Thanks!
> 
> Bo