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Message-ID: <aUmHRCXNy45PrVLG@redhat.com>
Date: Mon, 22 Dec 2025 13:00:36 -0500
From: Brian Masney <bmasney@...hat.com>
To: "irving.ch.lin" <irving-ch.lin@...iatek.com>
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Richard Cochran <richardcochran@...il.com>,
Qiqi Wang <qiqi.wang@...iatek.com>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-pm@...r.kernel.org,
netdev@...r.kernel.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
sirius.wang@...iatek.com, vince-wl.liu@...iatek.com,
jh.hsu@...iatek.com
Subject: Re: [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock
support
On Mon, Dec 15, 2025 at 11:49:13AM +0800, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@...iatek.com>
>
> Add support for the MT8189 apmixedsys clock controller, which provides
> PLLs generated from SoC 26m.
>
> Signed-off-by: Irving-CH Lin <irving-ch.lin@...iatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 13 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 192 +++++++++++++++++++
^^^^^^^^^^^^^^^^^^^^^^^
This file, along with others in this series, is not listed in
MAINTAINERS. This is the current entry:
MEDIATEK MT6735 CLOCK & RESET DRIVERS
M: Yassine Oudjana <y.oudjana@...tonmail.com>
L: linux-clk@...r.kernel.org
L: linux-mediatek@...ts.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c
F: drivers/clk/mediatek/clk-mt6735-imgsys.c
F: drivers/clk/mediatek/clk-mt6735-infracfg.c
F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c
F: drivers/clk/mediatek/clk-mt6735-pericfg.c
F: drivers/clk/mediatek/clk-mt6735-topckgen.c
F: drivers/clk/mediatek/clk-mt6735-vdecsys.c
F: drivers/clk/mediatek/clk-mt6735-vencsys.c
F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h
F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
Should the entries to MAINTAINERS be simplified to the following?
F: drivers/clk/mediatek/
F: include/dt-bindings/clock/mediatek,*
Brian
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