Message-ID: <20251222101112.aprpyfalend6jkhr@hu-kamalw-hyd.qualcomm.com>
Date: Mon, 22 Dec 2025 15:41:12 +0530
From: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>
Cc: Abel Vesa <abel.vesa@....qualcomm.com>,
        Pankaj Patil <pankaj.patil@....qualcomm.com>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        rajendra.nayak@....qualcomm.com, sibi.sankar@....qualcomm.com,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
        Maulik Shah <maulik.shah@....qualcomm.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>,
        Qiang Yu <qiang.yu@....qualcomm.com>,
        Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
        Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
        Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

Hi Bjorn,

On Sun, Dec 21, 2025 at 09:36:19PM -0600, Bjorn Andersson wrote:
> On Sun, Dec 21, 2025 at 05:17:34PM +0200, Abel Vesa wrote:
> > On 25-12-19 20:16:56, Pankaj Patil wrote:
> > > Introduce the base device tree support for Glymur – Qualcomm's
> > > next-generation compute SoC. The new glymur.dtsi describes the core SoC
> > > components, including:
> > > 
> > > - CPUs and CPU topology
> > > - Interrupt controller and TLMM
> > > - GCC,DISPCC and RPMHCC clock controllers
> > > - Reserved memory and interconnects
> > > - SMMU and firmware SCM
> > > - Watchdog, RPMHPD, APPS RSC and SRAM
> > > - PSCI and PMU nodes
> > > - QUPv3 serial engines
> > > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> > > - PDP0 mailbox, IPCC and AOSS
> > > - Display clock controller
> > > - SPMI PMIC arbiter with SPMI0/1/2 buses
> > > - SMP2P nodes
> > > - TSENS and thermal zones (8 instances, 92 sensors)
> > > 
> > > Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> > > PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
> > > 
> > > Add glmur-pmics.dtsi file for all the pmics enabled
> > > 
> > > Enabled PCIe controllers and associated PHY to support boot to
> > > shell with nvme storage,
> > > List of PCIe instances enabled:
> > > 
> > > - PCIe3b
> > > - PCIe4
> > > - PCIe5
> > > - PCIe6
> > > 
> > > Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > > Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > > Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > > Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > > Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > > Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> > > Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> > > Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > > Co-developed-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > > Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > > Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > > Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> > > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > > Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > > Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > > Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > > Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> > > ---
> > >  arch/arm64/boot/dts/qcom/glymur-pmics.dtsi   |   11 +
> > 
> > Separate patch for each file, please.
> > 
> 
> Why? We just told folks that we want the introduction of a new platform
> consolidated into 2-3 patches.
> And this would give us 6 small patches each one adding a trivial (and
> presumably incomplete) pmic files.
> 
> What I don't know though is why we have pmh0104-glymur.dtsi and
> pmh0110-glymur.dtsi, why are these "-glymur" ones? And why do we have
> glymur-pmics.dtsi? The times we've done <soc>-pmic.dtsi, we've put all
> the pmics in that one file, not just 6 includes...

Actually, we got this suggestion in the first series.
https://lore.kernel.org/all/b784387b-5744-422e-92f5-3d575a24d01c@kernel.org/ 
and at that time glymur-pmics.dtsi was still there.

Main reason for this was that Glymur has lot of PMICs and some of them are
as-is shared with Kaanapali (like pmk8850.dtsi & pmh0101.dtsi), and some have
been moved to different SID on Glymur (compared to Kaanapali) which needed the
-glymur.dtsi postfix and having the glymur-pmics.dtsi helps us in quickly
checking all that in one place.

We would prefer to have the pmic files seperate (then to have all in one
-pmics.dtsi) to get a clearer sense of the "leverage" between different chips.
In future too, we expect we will have lot of sharing of older pmic files in
future as well. So having seperate DT will be preferable for us.

That being said, if you want we can do away with the glymur-pmic.dtsi, and have
all the 6 includes directly in glymur-crd.dts? or if we can get a waiver? we
can keep the same approch ( having <soc>-pmics.dtsi and pmic.dtsi) going
forward on all future targets.

> 
> Regards,
> Bjorn
> 
> > Abel

Regards,
Kamal

Powered by blists - more mailing lists