| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20251222102400.1109-11-yuanjie.yang@oss.qualcomm.com>
Date: Mon, 22 Dec 2025 18:23:59 +0800
From: yuanjie yang <yuanjie.yang@....qualcomm.com>
To: robin.clark@....qualcomm.com, lumag@...nel.org, jesszhan0024@...il.com,
sean@...rly.run, marijn.suijten@...ainline.org, airlied@...il.com,
simona@...ll.ch, maarten.lankhorst@...ux.intel.com, mripard@...nel.org,
tzimmermann@...e.de, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, neil.armstrong@...aro.org,
konrad.dybcio@....qualcomm.com
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, tingwei.zhang@....qualcomm.com,
aiqun.yu@....qualcomm.com, yongxing.mou@....qualcomm.com
Subject: [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support
From: Yuanjie Yang <yuanjie.yang@....qualcomm.com>
Add support for Kaanapali platform SSPP sub-blocks, which
introduce structural changes including register additions,
removals, and relocations. Add the new common and rectangle
blocks, and update register definitions and handling to
ensure compatibility with DPU v13.0.
Co-developed-by: Yongxing Mou <yongxing.mou@....qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@....qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@....qualcomm.com>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
7 files changed, 371 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 8aa7d07303fb..8b94c5f1cb68 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -86,6 +86,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_hw_lm.o \
disp/dpu1/dpu_hw_pingpong.o \
disp/dpu1/dpu_hw_sspp.o \
+ disp/dpu1/dpu_hw_sspp_v13.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_merge3d.o \
disp/dpu1/dpu_hw_top.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 197a2c584c73..c6d8d7fb3880 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -248,6 +248,7 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
u32 chroma_samp, unpack, src_format;
u32 opmode;
u32 fast_clear;
+ u8 core_major_ver = ctx->mdss_ver->core_major_ver;
c = &ctx->hw;
opmode = DPU_REG_READ(c, op_mode_off);
@@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format
if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
- DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
- DPU_FETCH_CONFIG_RESET_VALUE |
- ctx->ubwc->highest_bank_bit << 18);
+ if (core_major_ver < 13)
+ DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
+ DPU_FETCH_CONFIG_RESET_VALUE |
+ ctx->ubwc->highest_bank_bit << 18);
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
@@ -724,7 +726,10 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
hw_pipe->mdss_ver = mdss_rev;
- _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
+ if (mdss_rev->core_major_ver >= 13)
+ dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev);
+ else
+ _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
return hw_pipe;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index c6b19cb4d158..309af4183ba3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -383,5 +383,9 @@ void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
bool danger_safe_en, u32 ctrl_off);
+void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
+ unsigned long features,
+ const struct dpu_mdss_version *mdss_rev);
+
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
new file mode 100644
index 000000000000..e78a20b45300
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/printk.h>
+#include <linux/soc/qcom/ubwc.h>
+
+#include "dpu_hw_sspp.h"
+
+/* >= v13 DPU */
+/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
+/* Name Offset */
+#define SSPP_CMN_CLK_CTRL 0x0
+#define SSPP_CMN_CLK_STATUS 0x4
+#define SSPP_CMN_MULTI_REC_OP_MODE 0x10
+#define SSPP_CMN_ADDR_CONFIG 0x14
+#define SSPP_CMN_CAC_CTRL 0x20
+#define SSPP_CMN_SYS_CACHE_MODE 0x24
+#define SSPP_CMN_QOS_CTRL 0x28
+
+#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c
+#define SSPP_CMN_FILL_LEVELS 0x40
+#define SSPP_CMN_STATUS 0x44
+#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48
+#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c
+#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50
+#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c
+#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60
+#define SSPP_CMN_UNPACK_LINE_COUNT 0x64
+#define SSPP_CMN_TPG_CONTROL 0x68
+#define SSPP_CMN_TPG_CONFIG 0x6c
+#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70
+#define SSPP_CMN_TPG_RECTANGLE 0x74
+#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78
+#define SSPP_CMN_TPG_RGB_MAPPING 0x7c
+#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80
+
+/*RECRegisterset*/
+/*Name Offset*/
+#define SSPP_REC_SRC_FORMAT 0x0
+#define SSPP_REC_SRC_UNPACK_PATTERN 0x4
+#define SSPP_REC_SRC_OP_MODE 0x8
+#define SSPP_REC_SRC_CONSTANT_COLOR 0xc
+#define SSPP_REC_SRC_IMG_SIZE 0x10
+#define SSPP_REC_SRC_SIZE 0x14
+#define SSPP_REC_SRC_XY 0x18
+#define SSPP_REC_OUT_SIZE 0x1c
+#define SSPP_REC_OUT_XY 0x20
+#define SSPP_REC_SW_PIX_EXT_LR 0x24
+#define SSPP_REC_SW_PIX_EXT_TB 0x28
+#define SSPP_REC_SRC_SIZE_ODX 0x30
+#define SSPP_REC_SRC_XY_ODX 0x34
+#define SSPP_REC_OUT_SIZE_ODX 0x38
+#define SSPP_REC_OUT_XY_ODX 0x3c
+#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40
+#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44
+#define SSPP_REC_PRE_DOWN_SCALE 0x48
+#define SSPP_REC_SRC0_ADDR 0x4c
+#define SSPP_REC_SRC1_ADDR 0x50
+#define SSPP_REC_SRC2_ADDR 0x54
+#define SSPP_REC_SRC3_ADDR 0x58
+#define SSPP_REC_SRC_YSTRIDE0 0x5c
+#define SSPP_REC_SRC_YSTRIDE1 0x60
+#define SSPP_REC_CURRENT_SRC0_ADDR 0x64
+#define SSPP_REC_CURRENT_SRC1_ADDR 0x68
+#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c
+#define SSPP_REC_CURRENT_SRC3_ADDR 0x70
+#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74
+#define SSPP_REC_CDP_CNTL 0x78
+#define SSPP_REC_TRAFFIC_SHAPER 0x7c
+#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80
+#define SSPP_REC_PD_MEM_ALLOC 0x84
+#define SSPP_REC_QOS_CLAMP 0x88
+#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c
+#define SSPP_REC_UBWC_STATIC_CTRL 0x90
+#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94
+#define SSPP_REC_UBWC_STATS_ROI 0x98
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8
+#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac
+#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0
+#define SSPP_REC_EXCL_REC_CTRL 0xb4
+#define SSPP_REC_EXCL_REC_SIZE 0xb8
+#define SSPP_REC_EXCL_REC_XY 0xbc
+#define SSPP_REC_LINE_INSERTION_CTRL 0xc0
+#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4
+#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8
+#define SSPP_REC_META_ERROR_STATUS 0xcc
+#define SSPP_REC_UBWC_ERROR_STATUS 0xd0
+#define SSPP_REC_FLUSH_CTRL 0xd4
+#define SSPP_REC_INTR_EN 0xd8
+#define SSPP_REC_INTR_STATUS 0xdc
+#define SSPP_REC_INTR_CLEAR 0xe0
+#define SSPP_REC_HSYNC_STATUS 0xe4
+#define SSPP_REC_FP16_CONFIG 0x150
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164
+#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170
+#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174
+#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178
+
+static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,
+ struct dpu_hw_sspp *ctx)
+{
+ return (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) ?
+ ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base;
+}
+
+static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+
+ if (!ctx)
+ return;
+
+ dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE);
+}
+
+static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe,
+ const struct msm_format *fmt, u32 flags)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 op_mode_off, unpack_pat_off, format_off;
+ u32 ubwc_ctrl_off, ubwc_err_off;
+ u32 offset;
+
+ if (!ctx || !fmt)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ op_mode_off = offset + SSPP_REC_SRC_OP_MODE;
+ unpack_pat_off = offset + SSPP_REC_SRC_UNPACK_PATTERN;
+ format_off = offset + SSPP_REC_SRC_FORMAT;
+ ubwc_ctrl_off = offset + SSPP_REC_UBWC_STATIC_CTRL;
+ ubwc_err_off = offset + SSPP_REC_UBWC_ERROR_STATUS;
+
+ dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
+ unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off);
+}
+
+static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_pixel_ext *pe_ext)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u8 color;
+ u32 lr_pe[4], tb_pe[4];
+ const u32 bytemask = 0xff;
+ u32 offset = ctx->cap->sblk->sspp_rec0_blk.base;
+
+ if (!ctx || !pe_ext)
+ return;
+
+ c = &ctx->hw;
+ /* program SW pixel extension override for all pipes*/
+ for (color = 0; color < DPU_MAX_PLANES; color++) {
+ /* color 2 has the same set of registers as color 1 */
+ if (color == 2)
+ continue;
+
+ lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24) |
+ ((pe_ext->right_rpt[color] & bytemask) << 16) |
+ ((pe_ext->left_ftch[color] & bytemask) << 8) |
+ (pe_ext->left_rpt[color] & bytemask);
+
+ tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24) |
+ ((pe_ext->btm_rpt[color] & bytemask) << 16) |
+ ((pe_ext->top_ftch[color] & bytemask) << 8) |
+ (pe_ext->top_rpt[color] & bytemask);
+ }
+
+ /* color 0 */
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);
+
+ /* color 1 and color 2 */
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);
+ DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);
+}
+
+static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe,
+ struct dpu_sw_pipe_cfg *cfg)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
+ u32 offset;
+
+ if (!ctx || !cfg)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ src_size_off = offset + SSPP_REC_SRC_SIZE;
+ src_xy_off = offset + SSPP_REC_SRC_XY;
+ out_size_off = offset + SSPP_REC_OUT_SIZE;
+ out_xy_off = offset + SSPP_REC_OUT_XY;
+
+ dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
+ src_xy_off, out_size_off, out_xy_off);
+}
+
+static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_fmt_layout *layout)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ int i;
+ u32 offset, ystride0, ystride1;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+
+ for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,
+ layout->plane_addr[i]);
+
+ ystride0 = (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16);
+ ystride1 = (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16);
+
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);
+ DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);
+}
+
+static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 color)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 const_clr_off;
+ u32 offset;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+ const_clr_off = offset + SSPP_REC_SRC_CONSTANT_COLOR;
+
+ dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
+}
+
+static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_qos_cfg *cfg)
+{
+ if (!ctx || !cfg)
+ return;
+
+ _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
+}
+
+static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en)
+{
+ if (!ctx)
+ return;
+
+ dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL);
+}
+
+static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe,
+ const struct msm_format *fmt,
+ bool enable)
+{
+ struct dpu_hw_sspp *ctx = pipe->sspp;
+ u32 offset = 0;
+
+ if (!ctx)
+ return;
+
+ offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
+ dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable);
+}
+
+static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, bool enable)
+{
+ static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
+ .reg_off = SSPP_CMN_CLK_CTRL,
+ .bit_off = 0
+ };
+
+ return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
+}
+
+void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
+ unsigned long features, const struct dpu_mdss_version *mdss_rev)
+{
+ c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
+ c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
+ c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress_v13;
+ c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
+ c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
+
+ if (test_bit(DPU_SSPP_QOS, &features)) {
+ c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut_v13;
+ c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl_v13;
+ }
+
+ if (test_bit(DPU_SSPP_CSC, &features) ||
+ test_bit(DPU_SSPP_CSC_10BIT, &features))
+ c->ops.setup_csc = dpu_hw_sspp_setup_csc;
+
+ if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
+ test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
+ c->ops.setup_multirect = dpu_hw_sspp_setup_multirect_v13;
+
+ if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
+ c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
+
+ if (test_bit(DPU_SSPP_CDP, &features))
+ c->ops.setup_cdp = dpu_hw_sspp_setup_cdp_v13;
+
+ c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl_v13;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 486be346d40d..3cf22ec62792 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
#define QOS_CREQ_LUT_0 0x14
#define QOS_CREQ_LUT_1 0x18
+/* CMN_QOS_LUT */
+#define SSPP_CMN_QOS_CTRL 0x28
+#define SSPP_CMN_DANGER_LUT 0x2c
+#define SSPP_CMN_SAFE_LUT 0x30
+#define SSPP_CMN_CREQ_LUT_0 0x34
+#define SSPP_CMN_CREQ_LUT_1 0x38
+
/* QOS_QOS_CTRL */
#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
@@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
}
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg)
+{
+ DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
+ DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
+ cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
+}
+
/*
* note: Aside from encoders, input_sel should be set to 0x0 by default
*/
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 67b08e99335d..1822ac699757 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
bool qos_8lvl,
const struct dpu_hw_qos_cfg *cfg);
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg);
+
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u8 input_sel);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 478a091aeccf..006dcc4a0dcc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
cfg);
}
+static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
+ struct dpu_hw_qos_cfg *cfg)
+{
+ if (!ctx || !cfg)
+ return;
+
+ _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
+}
+
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
const struct msm_format *fmt,
bool enable)
@@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
ops->setup_roi = dpu_hw_wb_roi;
- if (test_bit(DPU_WB_QOS, &features))
- ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ if (test_bit(DPU_WB_QOS, &features)) {
+ if (mdss_rev->core_major_ver >= 13)
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
+ else
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ }
if (test_bit(DPU_WB_CDP, &features))
ops->setup_cdp = dpu_hw_wb_setup_cdp;
--
2.34.1
Powered by blists - more mailing lists