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Message-Id: <176651187342.759340.7650219710991415977.b4-ty@kernel.org>
Date: Tue, 23 Dec 2025 23:14:33 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Neil Armstrong <neil.armstrong@...aro.org>, 
 Heiko Stuebner <heiko@...ech.de>, Dmitry Baryshkov <lumag@...nel.org>, 
 Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
Cc: kernel@...labora.com, linux-phy@...ts.infradead.org, 
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, 
 linux-kernel@...r.kernel.org, Derek Foreman <derek.foreman@...labora.com>
Subject: Re: [PATCH v2 0/2] Fixup HDMI PLL for phy-rockchip-samsung-hdptx


On Sun, 21 Dec 2025 12:36:22 +0200, Cristian Ciocaltea wrote:
> The Samsung HDMI/eDP TX PHY is currently not able to provide an accurate
> enough PLL output frequency to match the TMDS rate of a 1080p@...Hz
> display mode, when used with 10 bpc RGB.
> 
> This patch set adds a new entry to the TMDS configuration table,
> providing the necessary frequency division coefficients for the PHY PLL
> to generate the expected 461.101250 MHz output.
> 
> [...]

Applied, thanks!

[1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output
      commit: f2daf0c67a1767ff6536aa3e96599afb42ca42e7
[2/2] phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table
      commit: 3be8131ee936abb6ff56ca9ec9d38c911251410b

Best regards,
-- 
~Vinod



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