linux-kernel - Re: [PATCH v5 phy 00/15] Lynx 28G improvements part 1

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Message-Id: <176651192278.759340.10484878366738732561.b4-ty@kernel.org>
Date: Tue, 23 Dec 2025 23:15:22 +0530
From: Vinod Koul <vkoul@...nel.org>
To: linux-phy@...ts.infradead.org, 
 Vladimir Oltean <vladimir.oltean@....com>
Cc: Ioana Ciornei <ioana.ciornei@....com>, 
 Kishon Vijay Abraham I <kishon@...nel.org>, 
 Neil Armstrong <neil.armstrong@...aro.org>, 
 Josua Mayer <josua@...id-run.com>, linux-kernel@...r.kernel.org, 
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH v5 phy 00/15] Lynx 28G improvements part 1


On Tue, 25 Nov 2025 13:48:32 +0200, Vladimir Oltean wrote:
> This is the first part in upstreaming a set of around 100 patches that
> were developed in NXP's vendor Linux Factory kernel over the course of
> several years.
> 
> This part is mainly concerned with correcting some historical mistakes
> which make extending the driver more difficult:
> - The 3 instances of this SerDes block, as seen on NXP LX2160A, need to
>   be differentiated in order to reject configurations unsupported by
>   hardware. The proposal is to do that based on compatible string.
> - Lanes cannot have electrical parameters described in the device tree,
>   because they are not described in the device tree.
> - The register naming scheme forces us to modify a single register field
>   per lynx_28g_lane_rmw() call - leads to inefficient code
> - lynx_28g_lane_set_sgmii(), lynx_28g_lane_set_10gbaser() are unfit for
>   their required roles when the current SerDes protocol is 25GBase-R.
>   They are replaced with a better structured approach.
> - USXGMII and 10GBase-R have different protocol converters, and should
>   be treated separately by the SerDes driver.
> 
> [...]

Applied, thanks!

[01/15] dt-bindings: phy: lynx-28g: permit lane OF PHY providers
        commit: bd2f0117c2a1310dc6ea4eed8087eb2c6c03fe78
[02/15] phy: lynx-28g: refactor lane probing to lynx_28g_probe_lane()
        commit: a125feee0774e13914601dd6b39c73a27265f7d4
[03/15] phy: lynx-28g: support individual lanes as OF PHY providers
        commit: 7df7d58abbd60902751381dcd891a55c8228c523
[04/15] phy: lynx-28g: avoid memsetting lane already allocated with kzalloc()
        commit: 2da0b2214f511744a967d370447bb9d511bf1348
[05/15] phy: lynx-28g: remove LYNX_28G_ prefix from register names
        commit: 13a5f7e3fd6dbc49adb950592ba7d76f1211105d
[06/15] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask"
        commit: 6e3d3e8783ae41a7a678093591a2d93044b94ac0
[07/15] phy: lynx-28g: use FIELD_GET() and FIELD_PREP()
        commit: 3b84377c2a31cf35d33da55c6868281aa3aff71a
[08/15] phy: lynx-28g: convert iowrite32() calls with magic values to macros
        commit: 90d985a0eb33c92aa83a086bd934d885e2f4fd5b
[09/15] phy: lynx-28g: restructure protocol configuration register accesses
        commit: 6af3b6d365579a0b62d24e687f6d55d17f118172
[10/15] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic
        commit: 444bb9a7b3ef07ecb96ca7ae30a6c9daaf865de8
[11/15] phy: lynx-28g: refactor lane->interface to lane->mode
        commit: 6a1ae51896284de1a2387aaf2281ac01015277b5
[12/15] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII
        commit: 55ce1d64aa51baecdd26d56e3efb250c9671e988
[13/15] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE
        commit: 055d08beea2c1a1d0f4eccabbcf570009969e3ce
[14/15] phy: lynx-28g: use "dev" argument more in lynx_28g_probe()
        commit: 04dceaa3c97d3cdc51e1d78dce32ed7388872d07
[15/15] phy: lynx-28g: improve lynx_28g_probe() sequence
        commit: aecea96492f52364f852248055921c1b3aacbc91

Best regards,
-- 
~Vinod