linux-kernel - RE: [PATCH v6 3/8] dmaengine: sh: rz-dmac: Drop read of CHCTRL register

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Message-ID:
 <TY3PR01MB1134694D4CF924BDA7ECCCA7586B5A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Tue, 23 Dec 2025 14:25:22 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Claudiu.Beznea <claudiu.beznea@...on.dev>, "vkoul@...nel.org"
	<vkoul@...nel.org>, Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	"geert+renesas@...der.be" <geert+renesas@...der.be>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>
CC: Claudiu.Beznea <claudiu.beznea@...on.dev>, "dmaengine@...r.kernel.org"
	<dmaengine@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Claudiu Beznea
	<claudiu.beznea.uj@...renesas.com>
Subject: RE: [PATCH v6 3/8] dmaengine: sh: rz-dmac: Drop read of CHCTRL
 register

Hi Claudiu,

> -----Original Message-----
> From: Claudiu <claudiu.beznea@...on.dev>
> Sent: 23 December 2025 13:50
> Subject: [PATCH v6 3/8] dmaengine: sh: rz-dmac: Drop read of CHCTRL register
> 
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> The CHCTRL register has 11 bits that can be updated by software. The documentation for all these bits
> states the following:
> - A read operation results in 0 being read
> - Writing zero does not affect the operation
> 
> All bits in the CHCTRL register accessible by software are set and clear bits.
> 
> The documentation for the CLREND bit of CHCTRL states:
> Setting this bit to 1 can clear the END bit of the CHSTAT_n/nS register.
> Also, the DMA transfer end interrupt is cleared. An attempt to read this bit results in 0 being read.
> 1: Clears the END bit.
> 0: Does not affect the operation.
> 
> Since writing zero to any bit in this register does not affect controller operation and reads always
> return zero, there is no need to perform read-modify-write accesses to set the CLREND bit. Drop the
> read of the CHCTRL register.
> 
> Also, since setting the CLREND bit does not interact with other functionalities exposed through this
> register and only clears the END interrupt, there is no need to lock around this operation. Add a
> comment to document this.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Reviewed-by: Biju Das <biju.das.jz@...renesas.com>

Cheers,
Biju
> ---
> 
> Changes in v6:
> - none, this patch is new
> 
>  drivers/dma/sh/rz-dmac.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 818d1ef6f0bf..43a772e4478c
> 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -698,7 +698,7 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel)  {
>  	struct dma_chan *chan = &channel->vc.chan;
>  	struct rz_dmac *dmac = to_rz_dmac(chan->device);
> -	u32 chstat, chctrl;
> +	u32 chstat;
> 
>  	chstat = rz_dmac_ch_readl(channel, CHSTAT, 1);
>  	if (chstat & CHSTAT_ER) {
> @@ -710,8 +710,11 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel)
>  		goto done;
>  	}
> 
> -	chctrl = rz_dmac_ch_readl(channel, CHCTRL, 1);
> -	rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1);
> +	/*
> +	 * No need to lock. This just clears the END interrupt. Writing
> +	 * zeros to CHCTRL is just ignored by HW.
> +	 */
> +	rz_dmac_ch_writel(channel, CHCTRL_CLREND, CHCTRL, 1);
>  done:
>  	return;
>  }
> --
> 2.43.0