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Message-Id: <20251224-mtk-not-a-gate-v1-1-d4667e3b7856@collabora.com>
Date: Wed, 24 Dec 2025 08:30:10 +0100
From: Sjoerd Simons <sjoerd@...labora.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Jianhui Zhao <zhaojh329@...il.com>, Daniel Golle <daniel@...rotopia.org>,
Sam Shih <sam.shih@...iatek.com>, Ryder Lee <ryder.lee@...nel.org>
Cc: kernel@...labora.com, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, Sjoerd Simons <sjoerd@...labora.com>
Subject: [PATCH 1/4] clk: mediatek: clk-mux: Add helper for muxes without
UPD
Not all muxes have an update register. This is already handled by the
driver when the upd_shift field is set negative. Add a small helper
macro to declare these muxes, without having to pass a bunch of -1's.
Signed-off-by: Sjoerd Simons <sjoerd@...labora.com>
---
drivers/clk/mediatek/clk-mux.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
index 151e56dcf884..1a385cdd00d0 100644
--- a/drivers/clk/mediatek/clk-mux.h
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -126,6 +126,13 @@ extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
+#define MUX_CLR_SET(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width) \
+ GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ 0, 0, -1, CLK_SET_RATE_PARENT, \
+ mtk_mux_clr_set_upd_ops)
+
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
--
2.51.0
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